void init_mcbsp_spi()
{
// McBSP-A register settings
McbspaRegs.SPCR2.all=0x0000; // Reset FS generator, sample rate generator & transmitter
McbspaRegs.SPCR1.all=0x0000; // Reset Receiver, Right justify word, Digital loopback dis.
McbspaRegs.PCR.all=0x0F08; //(CLKXM=CLKRM=FSXM=FSRM= 1, FSXP = 1低电平有效)帧同步由DXR拷贝到XSR驱动
McbspaRegs.SPCR1.bit.DLB = 0;
McbspaRegs.SPCR1.bit.CLKSTP = 2; // 时钟停止模式Together with CLKXP/CLKRP determines clocking scheme
McbspaRegs.PCR.bit.CLKXP = 0; // CPOL = 0, CPHA = 0 rising edge no delay
McbspaRegs.PCR.bit.CLKRP = 0; //上升沿发送,下降沿接受
McbspaRegs.RCR2.bit.RDATDLY=01; // FSX setup time 1 in master mode. 0 for slave mode (Receive)
McbspaRegs.XCR2.bit.XDATDLY=01; // FSX setup time 1 in master mode. 0 for slave mode (Transmit)
McbspbRegs.XCR2.bit.XPHASE=0; //单相,每帧一个字,每字16位
McbspbRegs.RCR2.bit.RPHASE=0;
McbspbRegs.XCR1.bit.XFRLEN1=0;
McbspbRegs.RCR1.bit.RFRLEN1=0;
McbspaRegs.RCR1.bit.RWDLEN1=2; // 16-bit word
McbspaRegs.XCR1.bit.XWDLEN1=2; // 16-bit word
McbspaRegs.XCR2.bit.XFIG=0; //帧同步脉冲是否忽略,1=忽略
McbspaRegs.RCR2.bit.RFIG=0;
McbspaRegs.SRGR2.all=0x2013; // CLKSM=1,时钟来源于CPU,FSGM=0, 帧同步触发,FPER = 20 CLKG periods
McbspaRegs.SRGR1.all=0x0038; // Frame Width = 1 CLKG period, CLKGDV=16
McbspaRegs.SPCR2.bit.GRST=1; // Enable the sample rate generator
delay_loop(); // Wait at least 2 SRG clock cycles
McbspaRegs.SPCR2.bit.XRST=1; // Release TX from Reset
McbspaRegs.SPCR1.bit.RRST=1; // Release RX from Reset
delay_loop();
McbspaRegs.SPCR2.bit.FRST=1; // Frame Sync Generator reset
}
void mcbsp_xmit(int a)
{
McbspaRegs.DXR1.all=a;
}
for(;;)
{
while( McbspaRegs.SPCR2.bit.XRDY == 0 ) {}
mcbsp_xmit(table[i]);
while( McbspaRegs.SPCR2.bit.XRDY == 0 ) {}
while( McbspaRegs.SPCR2.bit.XEMPTY == 1 ) {}
}
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