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我用仿真器+ads调试，程序是从0x30000000开始执行：<br />30000000 [0xea000074] b ResetHandler<br />30000004 [0xea000052] b HandlerUndef<br />30000008 [0xea000057] b HandlerSWI<br />3000000c [0xea000062] b HandlerPabort<br />30000010 [0xea00005b] b HandlerDabort<br />30000014 [0xeafffffe] b 0x30000014<br />30000018 [0xea000047] b HandlerIRQ<br />3000001c [0xea000040] b HandlerFIQ<br />30000020 [0xea000008] b EnterPWDN<br />开始执行，我查看了地址0x000000处，如下：<br />00000000 [0xea00000a] b 0x30<br />00000004 [0xeafffffe] b 0x4<br />00000008 [0xeafffffe] b 0x8<br />0000000c [0xeafffffe] b 0xc<br />00000010 [0xeafffffe] b 0x10<br />00000014 [0xeafffffe] b 0x14<br />00000018 [0xeafffffe] b 0x18<br />0000001c [0xeafffffe] b 0x1c<br />当我触发中断后，发现中断的几个寄存器都有反应，但是程序跳到<br />00000018 [0xeafffffe] b 0x18<br />就不动了，请问怎样才能正确的跳转到<br />30000018 [0xea000047] b HandlerIRQ<br /><br /><br />我的启动代码如下。<br /><br /><br />;=========================================<br />; NAME: 2440INIT.S<br />; DESC: C start up codes<br />; Configure memory, ISR ,stacks<br />; Initialize C-variables<br />; HISTORY:<br />; 2002.02.25:kwtark: ver 0.0<br />; 2002.03.20:purnnamu: Add some functions for testing STOP,Sleep mode<br />; 2003.03.14:DonGo: Modified for 2440.<br />;=========================================<br /><br /> GET option.inc<br /> GET memcfg.inc<br /> GET 2440addr.inc<br /><br />BIT_SELFREFRESH EQU (1<<22)<br /><br />;Pre-defined constants<br />USERMODE EQU 0x10<br />FIQMODE EQU 0x11<br />IRQMODE EQU 0x12<br />SVCMODE EQU 0x13<br />ABORTMODE EQU 0x17<br />UNDEFMODE EQU 0x1b<br />MODEMASK EQU 0x1f<br />NOINT EQU 0xc0<br /><br />;The location of stacks<br />UserStack EQU (_STACK_BASEADDRESS-0x3800) ;0x33ff4800 ~<br />SVCStack EQU (_STACK_BASEADDRESS-0x2800) ;0x33ff5800 ~<br />UndefStack EQU (_STACK_BASEADDRESS-0x2400) ;0x33ff5c00 ~<br />AbortStack EQU (_STACK_BASEADDRESS-0x2000) ;0x33ff6000 ~<br />IRQStack EQU (_STACK_BASEADDRESS-0x1000) ;0x33ff7000 ~<br />FIQStack EQU (_STACK_BASEADDRESS-0x0) ;0x33ff8000 ~<br /><br />;Check if tasm.exe(armasm -16 ...@ADS 1.0) is used.<br /> GBLL THUMBCODE<br /> [ {CONFIG} = 16<br />THUMBCODE SETL {TRUE}<br /> CODE32<br /> |<br />THUMBCODE SETL {FALSE}<br /> ]<br /><br /> MACRO<br /> MOV_PC_LR<br /> [ THUMBCODE<br /> bx lr<br /> |<br /> mov pc,lr<br /> ]<br /> MEND<br /><br /> MACRO<br /> MOVEQ_PC_LR<br /> [ THUMBCODE<br /> bxeq lr<br /> |<br /> moveq pc,lr<br /> ]<br /> MEND<br /><br /> MACRO<br />$HandlerLabel HANDLER $HandleLabel<br /><br />$HandlerLabel<br /> sub sp,sp,#4 ;decrement sp(to store jump address)<br /> stmfd sp!,{r0} ;PUSH the work register to stack(lr does't push because it return to original address)<br /> ldr r0,=$HandleLabel;load the address of HandleXXX to r0<br /> ldr r0,[r0] ;load the contents(service routine start address) of HandleXXX<br /> str r0,[sp,#4] ;store the contents(ISR) of HandleXXX to stack<br /> ldmfd sp!,{r0,pc} ;POP the work register and pc(jump to ISR)<br /> MEND<br /><br /><br /> IMPORT |Image$$RO$$Limit| ; End of ROM code (=start of ROM data)<br /> IMPORT |Image$$RW$$Base| ; Base of RAM to initialise<br /> IMPORT |Image$$ZI$$Base| ; Base and limit of area<br /> IMPORT |Image$$ZI$$Limit| ; to zero initialise<br /><br /> IMPORT MMU_SetAsyncBusMode<br /><br /> AREA Init,CODE,READONLY<br /><br /> ENTRY<br /><br /> ;1)The code, which converts to Big-endian, should be in little endian code.<br /> ;2)The following little endian code will be compiled in Big-Endian mode.<br /> ; The code byte order should be changed as the memory bus width.<br /> ;3)The pseudo instruction,DCD can't be used here because the linker generates error.<br /> ASSERT :DEF:ENDIAN_CHANGE<br /> [ ENDIAN_CHANGE<br /> ASSERT :DEF:ENTRY_BUS_WIDTH<br /> ][ ENTRY_BUS_WIDTH=32<br /> b ChangeBigEndian ;DCD 0xea000007<br /> ]<br /><br /> [ ENTRY_BUS_WIDTH=16<br /> andeq r14,r7,r0,lsl #20 ;DCD 0x0007ea00<br /> ]<br /><br /> [ ENTRY_BUS_WIDTH=8<br /> streq r0,][r0,-r10,ror #1] ;DCD 0x070000ea<br /> ]<br /> |<br /> b ResetHandler<br /> ]<br /> b HandlerUndef ;handler for Undefined mode<br /> b HandlerSWI ;handler for SWI interrupt<br /> b HandlerPabort ;handler for PAbort<br /> b HandlerDabort ;handler for DAbort<br /> b . ;reserved<br /> b HandlerIRQ ;handler for IRQ interrupt<br /> b HandlerFIQ ;handler for FIQ interrupt<br /><br />;@0x20<br /> b EnterPWDN ; Must be @0x20.<br />ChangeBigEndian<br />;@0x24<br /> [ ENTRY_BUS_WIDTH=32<br /> DCD 0xee110f10 ;0xee110f10 => mrc p15,0,r0,c1,c0,0<br /> DCD 0xe3800080 ;0xe3800080 => orr r0,r0,#0x80; //Big-endian<br /> DCD 0xee010f10 ;0xee010f10 => mcr p15,0,r0,c1,c0,0<br /> ]<br /> [ ENTRY_BUS_WIDTH=16<br /> DCD 0x0f10ee11<br /> DCD 0x0080e380<br /> DCD 0x0f10ee01<br /> ]<br /> [ ENTRY_BUS_WIDTH=8<br /> DCD 0x100f11ee<br /> DCD 0x800080e3<br /> DCD 0x100f01ee<br /> ]<br /> DCD 0xffffffff ;swinv 0xffffff is similar with NOP and run well in both endian mode.<br /> DCD 0xffffffff<br /> DCD 0xffffffff<br /> DCD 0xffffffff<br /> DCD 0xffffffff<br /> b ResetHandler<br /><br />;Function for entering power down mode<br />; 1. SDRAM should be in self-refresh mode.<br />; 2. All interrupt should be maksked for SDRAM/DRAM self-refresh.<br />; 3. LCD controller should be disabled for SDRAM/DRAM self-refresh.<br />; 4. The I-cache may have to be turned on.<br />; 5. The location of the following code may have not to be changed.<br /><br />;void EnterPWDN(int CLKCON);<br />EnterPWDN<br /> mov r2,r0 ;r2=rCLKCON<br /> tst r0,#0x8 ;SLEEP mode?<br /> bne ENTER_SLEEP<br /><br />ENTER_STOP<br /> ldr r0,=REFRESH<br /> ldr r3,[r0] ;r3=rREFRESH<br /> mov r1, r3<br /> orr r1, r1, #BIT_SELFREFRESH<br /> str r1, [r0] ;Enable SDRAM self-refresh<br /><br /> mov r1,#16 ;wait until self-refresh is issued. may not be needed.<br />0 subs r1,r1,#1<br /> bne %B0<br /><br /> ldr r0,=CLKCON ;enter STOP mode.<br /> str r2,[r0]<br /><br /> mov r1,#32<br />0 subs r1,r1,#1 ;1) wait until the STOP mode is in effect.<br /> bne %B0 ;2) Or wait here until the CPU&Peripherals will be turned-off<br /> ; Entering SLEEP mode, only the reset by wake-up is available.<br /><br /> ldr r0,=REFRESH ;exit from SDRAM self refresh mode.<br /> str r3,[r0]<br /><br /> MOV_PC_LR<br /><br />ENTER_SLEEP<br /> ;NOTE.<br /> ;1) rGSTATUS3 should have the return address after wake-up from SLEEP mode.<br /><br /> ldr r0,=REFRESH<br /> ldr r1,[r0] ;r1=rREFRESH<br /> orr r1, r1, #BIT_SELFREFRESH<br /> str r1, [r0] ;Enable SDRAM self-refresh<br /><br /> mov r1,#16 ;Wait until self-refresh is issued,which may not be needed.<br />0 subs r1,r1,#1<br /> bne %B0<br /><br /> ldr r1,=MISCCR<br /> ldr r0,[r1]<br /> orr r0,r0,#(7<<17) ;Set SCLK0=0, SCLK1=0, SCKE=0.<br /> str r0,[r1]<br /><br /> ldr r0,=CLKCON ; Enter sleep mode<br /> str r2,[r0]<br /><br /> b . ;CPU will die here.<br /><br /><br />WAKEUP_SLEEP<br /> ;Release SCLKn after wake-up from the SLEEP mode.<br /> ldr r1,=MISCCR<br /> ldr r0,[r1]<br /> bic r0,r0,#(7<<17) ;SCLK0:0->SCLK, SCLK1:0->SCLK, SCKE:0->=SCKE.<br /> str r0,[r1]<br /><br /> ;Set memory control registers<br /> ldr r0,=SMRDATA<br /> ldr r1,=BWSCON ;BWSCON Address<br /> add r2, r0, #52 ;End address of SMRDATA<br />0<br /> ldr r3, [r0], #4<br /> str r3, [r1], #4<br /> cmp r2, r0<br /> bne %B0<br /><br /> mov r1,#256<br />0 subs r1,r1,#1 ;1) wait until the SelfRefresh is released.<br /> bne %B0<br /><br /> ldr r1,=GSTATUS3 ;GSTATUS3 has the start address just after SLEEP wake-up<br /> ldr r0,[r1]<br /><br /> mov pc,r0<br /><br /> LTORG<br />HandlerFIQ HANDLER HandleFIQ<br />HandlerIRQ HANDLER HandleIRQ<br />HandlerUndef HANDLER HandleUndef<br />HandlerSWI HANDLER HandleSWI<br />HandlerDabort HANDLER HandleDabort<br />HandlerPabort HANDLER HandlePabort<br /><br />IsrIRQ<br /> sub sp,sp,#4 ;reserved for PC<br /> stmfd sp!,{r8-r9}<br /><br /> ldr r9,=INTOFFSET ; 读取INTOFFSET的地址<br /> ldr r9,[r9] ; 读取INTOFFSET的数据<br /> ldr r8,=HandleEINT0 ; 读取HandleEINT0的地址<br /> add r8,r8,r9,lsl #2 ; r8=r8+(r9<<2)<br /> ldr r8,[r8]<br /> str r8,[sp,#8]<br /> ldmfd sp!,{r8-r9,pc}<br /><br />;=======<br />; ENTRY<br />;=======<br />ResetHandler<br /> ldr r0,=WTCON ;watch dog disable<br /> ldr r1,=0x0<br /> str r1,[r0]<br /><br /> ldr r0,=INTMSK<br /> ldr r1,=0xffffffff ;all interrupt disable<br /> str r1,[r0]<br /><br /> ldr r0,=INTSUBMSK<br /> ldr r1,=0x3ff ;all sub interrupt disable<br /> str r1,[r0]<br /><br /> [ {FALSE}<br /> ; rGPFDAT = (rGPFDAT & ~(0xf<<4)) | ((~data & 0xf)<<4);<br /> ; Led_Display<br /> ldr r0,=GPFCON<br /> ldr r1,=0x5500<br /> str r1,][r0]<br /> ldr r0,=GPFDAT<br /> ldr r1,=0x10<br /> str r1,[r0]<br /> ]<br /><br /> ;To reduce PLL lock time, adjust the LOCKTIME register.<br /> ldr r0,=LOCKTIME<br /> ldr r1,=0xffffff<br /> str r1,[r0]<br /><br /> [ PLL_ON_START<br /> ; Added for confirm clock divide. for 2440.<br /> ; Setting value Fclk:Hclk:Pclk<br /> ldr r0,=CLKDIVN <br /> ldr r1,=CLKDIV_VAL ; 0=1:1:1, 1=1:1:2, 2=1:2:2, 3=1:2:4, 4=1:4:4, 5=1:4:8, 6=1:3:3, 7=1:3:6.<br /> str r1,][r0]<br /><br /> [ CLKDIV_VAL>1 ; means Fclk:Hclk is not 1:1.<br /> bl MMU_SetAsyncBusMode<br /> |<br /> bl MMU_SetFastBusMode ; default value.<br /> ]<br /><br /> ;Configure UPLL<br /> ldr r0,=UPLLCON<br /> ;ldr r1,=((U_MDIV<<12)+(U_PDIV<<4)+U_SDIV)<br /> ldr r1, =((0x48<<12)+(0x3<<4)+0x2) ;tnt <br /> str r1,[r0]<br /> <br /> nop ; Caution: After UPLL setting, at least 7-clocks delay must be inserted for setting hardware be completed.<br /> nop<br /> nop<br /> nop<br /> nop<br /> nop<br /> nop<br /> ;Configure MPLL<br /> ldr r0,=MPLLCON<br /> ;ldr r1,=((M_MDIV<<12)+(M_PDIV<<4)+M_SDIV)<br /> ldr r1,=((0x7f<<12)+(0x2<<4)+0x1);tnt <br /> str r1,[r0]<br /> ]<br /> <br /> ;Check if the boot is caused by the wake-up from SLEEP mode.<br /> ldr r1,=GSTATUS2<br /> ldr r0,[r1]<br /> tst r0,#0x2<br /> ;In case of the wake-up from SLEEP mode, go to SLEEP_WAKEUP handler.<br /> bne WAKEUP_SLEEP<br /><br /> EXPORT StartPointAfterSleepWakeUp<br />StartPointAfterSleepWakeUp<br /> <br /> ;Set memory control registers<br /> ldr r0,=SMRDATA<br /> ldr r1,=BWSCON ;BWSCON Address<br /> add r2, r0, #52 ;End address of SMRDATA<br /><br /> <br />0<br /> ldr r3, [r0], #4<br /> str r3, [r1], #4<br /> cmp r2, r0<br /> bne %B0<br /><br /> ;Initialize stacks<br /> bl InitStacks<br /><br /><br /> ; Setup IRQ handler<br /> ldr r0,=HandleIRQ ;This routine is needed<br /> ldr r1,=IsrIRQ ;if there isn't 'subs pc,lr,#4' at 0x18, 0x1c<br /> str r1,[r0]<br /><br /><br /> ;If main() is used, the variable initialization will be done in __main().<br /> [ :LNOT:USE_MAIN <br /> ;Copy and paste RW data/zero initialized data<br /> LDR r0, =|Image$$RO$$Limit| ; Get pointer to ROM data<br /> LDR r1, =|Image$$RW$$Base| ; and RAM copy<br /> LDR r3, =|Image$$ZI$$Base| <br /> <br /> ;Zero init base => top of initialised data<br /> CMP r0, r1 ; Check that they are different<br /> BEQ %F2<br />1 <br /> CMP r1, r3 ; Copy init data<br /> LDRCC r2, ][r0], #4 ;--> LDRCC r2, [r0] + ADD r0, r0, #4 <br /> STRCC r2, [r1], #4 ;--> STRCC r2, [r1] + ADD r1, r1, #4<br /> BCC %B1<br />2 <br /> LDR r1, =|Image$$ZI$$Limit| ; Top of zero init segment<br /> MOV r2, #0<br />3 <br /> CMP r3, r1 ; Zero init<br /> STRCC r2, [r3], #4<br /> BCC %B3<br /> ]<br /><br /><br /> GBLS MAIN<br /> [ USE_MAIN<br /> IMPORT __main<br />MAIN SETS "__main"<br /> |<br /> IMPORT CEntry <br />MAIN SETS "CEntry"<br /> ] <br /><br /><br /> [ :LNOT:THUMBCODE<br /> BL $MAIN <br /> B . <br /> ]<br /><br /> [ THUMBCODE ;for start-up code for Thumb mode<br /> orr lr,pc,#1<br /> bx lr<br /> CODE16<br /> bl $MAIN <br /> b .<br /> CODE32<br /> ]<br /><br /><br />;function initializing stacks<br />InitStacks<br /> ;Don't use DRAM,such as stmfd,ldmfd......<br /> ;SVCstack is initialized before<br /> ;Under toolkit ver 2.5, 'msr cpsr,r1' can be used instead of 'msr cpsr_cxsf,r1'<br /> mrs r0,cpsr<br /> bic r0,r0,#MODEMASK<br /> orr r1,r0,#UNDEFMODE|NOINT<br /> msr cpsr_cxsf,r1 ;UndefMode<br /> ldr sp,=UndefStack ; UndefStack=0x33FF_5C00<br /><br /> orr r1,r0,#ABORTMODE|NOINT<br /> msr cpsr_cxsf,r1 ;AbortMode<br /> ldr sp,=AbortStack ; AbortStack=0x33FF_6000<br /><br /> orr r1,r0,#IRQMODE|NOINT<br /> msr cpsr_cxsf,r1 ;IRQMode<br /> ldr sp,=IRQStack ; IRQStack=0x33FF_7000<br /><br /> orr r1,r0,#FIQMODE|NOINT<br /> msr cpsr_cxsf,r1 ;FIQMode<br /> ldr sp,=FIQStack ; FIQStack=0x33FF_8000<br /><br /> bic r0,r0,#MODEMASK|NOINT<br /> orr r1,r0,#SVCMODE<br /> msr cpsr_cxsf,r1 ;SVCMode<br /> ldr sp,=SVCStack ; SVCStack=0x33FF_5800<br /><br /> ;USER mode has not be initialized.<br /><br /> mov pc,lr<br /> ;The LR register won't be valid if the current mode is not SVC mode.<br /><br /> <br />;=====================================================================<br />; Clock division test<br />; Assemble code, because VSYNC time is very short<br />;=====================================================================<br /> EXPORT CLKDIV124<br /> EXPORT CLKDIV144<br /> <br />CLKDIV124<br /> <br /> ldr r0, = CLKDIVN<br /> ldr r1, = 0x3 ; 0x3 = 1:2:4<br /> str r1, [r0]<br />; wait until clock is stable<br /> nop<br /> nop<br /> nop<br /> nop<br /> nop<br /><br /> ldr r0, = REFRESH<br /> ldr r1, [r0]<br /> bic r1, r1, #0xff<br /> bic r1, r1, #(0x7<<8)<br /> orr r1, r1, #0x470 ; REFCNT135<br /> str r1, [r0]<br /> nop<br /> nop<br /> nop<br /> nop<br /> nop<br /> mov pc, lr<br /><br />CLKDIV144<br /> ldr r0, = CLKDIVN<br /> ldr r1, = 0x4 ; 0x4 = 1:4:4<br /> str r1, [r0]<br />; wait until clock is stable<br /> nop<br /> nop<br /> nop<br /> nop<br /> nop<br /><br /> ldr r0, = REFRESH<br /> ldr r1, [r0]<br /> bic r1, r1, #0xff<br /> bic r1, r1, #(0x7<<8)<br /> orr r1, r1, #0x630 ; REFCNT675 - 1520<br /> str r1, [r0]<br /> nop<br /> nop<br /> nop<br /> nop<br /> nop<br /> mov pc, lr<br /><br /><br /> LTORG<br /><br />SMRDATA DATA<br />; Memory configuration should be optimized for best performance<br />; The following parameter is not optimized.<br />; Memory access cycle parameter strategy<br />; 1) The memory settings is safe parameters even at HCLK=75Mhz.<br />; 2) SDRAM refresh period is for HCLK<=75Mhz.<br /><br /> DCD (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))<br /> DCD ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) ;GCS0<br /> DCD ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) ;GCS1<br /> DCD ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) ;GCS2<br /> DCD ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) ;GCS3<br /> DCD ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) ;GCS4<br /> DCD ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) ;GCS5<br /> DCD ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) ;GCS6<br /> DCD ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) ;GCS7<br /> DCD ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)<br /><br /> DCD 0x32 ;SCLK power saving mode, BANKSIZE 128M/128M<br /><br /> DCD 0x30 ;MRSR6 CL=3clk<br /> DCD 0x30 ;MRSR7 CL=3clk<br /><br /><br /> ALIGN<br /><br /> AREA RamData, DATA, READWRITE<br /><br /> ^ _ISR_STARTADDRESS ; _ISR_STARTADDRESS=0x33FF_FF00<br />HandleReset # 4<br />HandleUndef # 4<br />HandleSWI # 4<br />HandlePabort # 4<br />HandleDabort # 4<br />HandleReserved # 4<br />HandleIRQ # 4 <br />HandleFIQ # 4<br /><br />;Don't use the label 'IntVectorTable',<br />;The value of IntVectorTable is different with the address you think it may be.<br />;IntVectorTable<br />;@0x33FF_FF20<br />HandleEINT0 # 4<br />HandleEINT1 # 4<br />HandleEINT2 # 4<br />HandleEINT3 # 4<br />HandleEINT4_7 # 4<br />HandleEINT8_23 # 4<br />HandleCAM # 4 ; Added for 2440.<br />HandleBATFLT # 4<br />HandleTICK # 4<br />HandleWDT # 4<br />HandleTIMER0 # 4<br />HandleTIMER1 # 4<br />HandleTIMER2 # 4<br />HandleTIMER3 # 4<br />HandleTIMER4 # 4<br />HandleUART2 # 4<br />;@0x33FF_FF60<br />HandleLCD # 4<br />HandleDMA0 # 4<br />HandleDMA1 # 4<br />HandleDMA2 # 4<br />HandleDMA3 # 4<br />HandleMMC # 4<br />HandleSPI0 # 4<br />HandleUART1 # 4<br />HandleNFCON # 4 ; Added for 2440.<br />HandleUSBD # 4<br />HandleUSBH # 4<br />HandleIIC # 4<br />HandleUART0 # 4<br />HandleSPI1 # 4<br />HandleRTC # 4<br />HandleADC # 4<br />;@0x33FF_FFA0<br /> END<br /> |
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