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请教双向口的testbench<br />我用verilog写了个双向口,程序如下:<br /><br />// test.v<br />module test(xck, d_port, inp, outp, dir);<br />input xck;<br />inout [7:0] d_port;<br />input [7:0] inp;<br />output[7:0] outp;<br />input dir;<br /><br />reg [7:0] outpTemp;<br />reg [7:0] d_portTemp;<br /><br />assign outp=outpTemp;<br />assign d_port=dir?d_portTemp:8'bzzzzzzzz;<br /><br />[email=always@(posedge]always@(posedge[/email] xck)<br />begin<br /> if(dir) // dir=1 做输出<br /> d_portTemp <=inp; <br /> else // dir=0 输入<br /> outpTemp<=d_portTemp;<br />end<br />endmodule<br /><br /><br />双向口的方向由dir控制.<br />testbench程序如下:<br />/*********************************** <br />** 模块名称：testbench <br />** 模块功能：产生测试激励向量 <br />************************************/ <br /><br />`timescale 1 ns / 1 ns <br />module testbench(); //模块名命名为Libero默认的testbench <br />reg clk; <br />reg dir; <br />reg [7:0] tempp;<br />reg [7:0] in_temp;<br />wire [7:0] out_temp;<br />parameter period = 20 ; //测试时钟频率周期20ns <br />always #(period/2) clk = ~clk; //产生测试时钟 <br />initial <br />begin <br /> clk = 0;<br /> dir = 1; <br /> #20000 dir = 0;<br /> in_temp=8'haa;<br /> #4000 in_temp=8'hbb;<br /> #8000 in_temp=8'hcc;<br /> #12000 in_temp=8'hdd;<br /> #16000 in_temp=8'hee;<br /> #20000 in_temp=8'h55;<br /><br /> tempp=8'h00;<br /> #20000 tempp=8'haa;<br /> #24000 tempp=8'hbb;<br /> #28000 tempp=8'hcc;<br /> #32000 tempp=8'hdd;<br /> #34000 tempp=8'hee;<br /> #40000 tempp=8'h55;<br />end <br /><br />test test_0(.xck(clk),.d_port(tempp),.inp(in_temp),.outp(out_temp),.dir(dir)); <br /><br />endmodule<br /><br />我想在前20000ns时, dir为1, 双向口做位输出口, 后20000ns双向口做输入.<br /><br />modelsim编译时提示tempp 口有问题, 但我不知道原因<br /><br />请大家指点,谢谢! |
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