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--代码如下:<br />library ieee;<br />use ieee.std_logic_1164.all;<br />use ieee.std_logic_unsigned.all;<br /><br />entity counter is<br />port (data :in std_logic_vector (7 downto 0);<br /> a,clk,clr,en :in std_logic;<br /> mm :out std_logic_vector (7 downto 0));<br />end;<br /><br />architecture AA of counter is<br />signal hold: std_logic_vector (7 downto 0);<br />begin<br /> process(clk)<br /> variable change :std_logic_vector (7 downto 0);<br /> begin<br /><br /> if (clk'event and clk='1') then<br /> if clr='0' then<br /> change:="00000000";<br /> elsif en='1' then<br /> <br /> if a='1' then<br /> change:=change+data; --其初始值为如何？<br /> <br /> if ((change(3)='1') and ((change(2)='1') or<br /> (change(1)='1'))) or <br /> (not(hold(7 downto 4)=change(7 downto 4)-data(7 downto 4))) then<br /> change:=change+6;<br /> end if;<br /> <br /> if ((change(7)='1') and ((change(6)='1') or (change(5)='1'))) then<br /> change:="00000000";<br /> end if;<br /><br /> else<br /> change:=change-data;<br /> <br /> if ((change(3)='1') and ((change(2)='1') or (change(1)='1'))) or (not(hold(7 downto 4)=change(7 downto 4)-data(7 downto 4))) then<br /> change:=change-6;<br /> end if;<br /> <br /> if ((change(7)='1') and ((change(6)='1') or (change(5)='1'))) then<br /> change:="00000000";<br /> end if;<br /> end if;<br /> end if;<br /> end if;<br /> mm<=change; --如果是不允许呢？change 即：variable 的初始值如何？<br /> hold<=change;<br /> end process;<br />end aa;<br /><br /> |
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楼主
