下面是官方勘误手册上对这两个bug的描述，我现在想知道的是怎么用变通的方法规避这个bug而不换芯片
FIFO_INFO command does not update TX_FIFO_ALMOST_EMPTY status properly
Description: If the TX FIFO is reset by the FIFO_INFO command, the chip does not update the TX_FIFO_ALMOST_EMPTY status bit correctly. It gets updated only by the next TX FIFO fill that causes the TX_FIFO_ALMOST_EMPTY interrupt to occur later than expected.
Impact: TX_FIFO_ALMOST_EMPTY interrupt occurs later than expected.
Workaround: Write one dummy byte into the TX_FIFO to fire the TX_FIFO_ALMOST_EMPTY interrupt and reset the TX_FIFO again. A fix has been identified and will be included in the next revision of the device.
FIFO Threshold Limitations
Description: Threshold of TX_FIFO_ALMOST_EMPTY interrupt can only be set to as high as 58 bytes for reliable interrupt generation when the threshold is reached. If the payload length of the transmitted packet is less than 7 bytes, the user can rely on the PACKET_SENT interrupt which indicates the end of packet transmission. Threshold of RX_FIFO_ALMOST_FULL interrupt can only be set to as low as 12 bytes for reliable interrupt generation when the threshold is reached. If the payload length of the received packet is less than 12 bytes, the user can rely on the PACKET_RX interrupt which indicates the end of packet.
Impact: User should not rely on FIFO threshold interrupts for greater than 58 bytes on the TX side and less than 12 bytes on the RX side.
Workaround: Rely on PACKET_SENT and PACKET_RX interrupts for very small payload lengths as described above. A fix has been identified and will be included in the next revision of the device.
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