如何指定一个时钟分配到全局网络或确定的象限全局网络上。
如，我想把clk_or指定到象限全局上，应该怎么实现。
module test
( clk_A,
clk_B,
clk,
rst_n,
count
);
input clk_A;
input clk_B;
input rst_n;
input clk;
output [31:0] count;
reg tamp_a0,tamp_b0,tamp_a1,tamp_b1;
reg [31:0] count;
reg [31:0] count_q;
wire clk_AA;
wire clk_BB;
wire clk_or;
wire clk_or_in;
CLKINT u_clk_or(
.Y (clk_or),
.A (clk_or_in)
);
assign clk_or_in = clk_AA|clk_BB;
assign clk_AA = tamp_a0^tamp_a1;
assign clk_BB = tamp_b0^tamp_b1;
always @(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
tamp_a0 <= 0;
tamp_a1 <= 0;
end
else
begin
tamp_a0 <= clk_A;
tamp_a1 <= tamp_a0;
end
end
always @(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
tamp_b0 <= 0;
tamp_b1 <= 0;
end
else
begin
tamp_b0 <= clk_B;
tamp_b1 <= tamp_b0;
end
end
always @(posedge clk_or or negedge rst_n)
begin
if(!rst_n)
count_q <=32'b0;
else
begin
case({tamp_a0,tamp_a1,tamp_b0,tamp_b1})
4'b1000,4'b0111,4'b1110,4'b0001: count_q <= count_q + 1;
4'b1011,4'b0100,4'b0010,4'b1101: count_q <= count_q - 1;
default:count_q <= count_q;
endcase
end
end
always @(posedge clk or negedge rst_n)
begin
if(!rst_n)
count <=32'b0;
else
count <= count_q;
end
endmodule
|
|
楼主
