frameBuffer24BitTft640480=(U32 (*)[SCR_XSIZE_TFT_640480])LCDFRAMEBUFFER;
rLCDCON1=(CLKVAL_TFT_640480<<8)|(MVAL_USED<<7)|(3<<5)|(13<<1)|0;
// TFT LCD panel,24bpp TFT,ENVID=off
rLCDCON2=(VBPD_640480<<24)|(LINEVAL_TFT_640480<<14)|(VFPD_640480<<6)|(VSPW_640480);
rLCDCON3=(HBPD_640480<<19)|(HOZVAL_TFT_640480<<8)|(HFPD_640480);
rLCDCON4=(MVAL<<8)|(HSPW_640480);
rLCDCON5=(1<<12)|(1<<9)|(1<<8); // BPP24:MSB,HSYNC and VSYNC are inverted
rLCDSADDR1=(((U32)frameBuffer24BitTft640480>>22)<<21)|M5D((U32)frameBuffer24BitTft640480>>1);
rLCDSADDR2=M5D( ((U32)frameBuffer24BitTft640480+(SCR_XSIZE_TFT_640480*LCD_YSIZE_TFT_640480*4))>>1 );
rLCDSADDR3=(((SCR_XSIZE_TFT_640480-LCD_XSIZE_TFT_640480)*2)<<11)|(LCD_XSIZE_TFT_640480*2);
rLCDINTMSK|=(3); // MASK LCD Sub Interrupt
rTCONSEL &=(~7); // Disable LPC3600
rTPAL=0; // Disable Temp Palette
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