parameter idle=2'b00;
parameter write_state=2'b01;
parameter read_state=2'b10;
reg [1:0]current_state;
reg [1:0]next_state;
reg [1:0]cnt;
reg [9:0]init_cnt;
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
current_state<=idle;
else
current_state<=next_state;
end
always@(*)
begin
case(current_state)
idle:begin
if(init_cnt==10'd1023)
next_state=write_state;
else
next_state<=idle;
end
write_state:begin
if((addr==17'h1fffe)&(cnt==2'b11))
next_state<=read_state;
else
next_state<=write_state;
end
read_state:begin
if((addr==17'h1fffe)&(cnt==2'b11))
next_state<=idle;
else
next_state<=read_state;
end
default:
next_state<=idle;
endcase
end
always@(posedge clk or negedge rst_n)begin
if(!rst_n)begin
addr<=17'h0;
oe<=1'b1;
wr<=1'b1;
cnt<=2'b0;
init_cnt<=10'h0;
end
else begin
case(current_state)
idle:begin
addr<=17'h0;
oe<=1'b1;
wr<=1'b1;
ce<=1'b1;
write_data<=8'h0;
read_data<=8'h0;
if(init_cnt==10'd1023)
init_cnt<=10'd1023;
else
init_cnt<=init_cnt+1;
end
write_state:begin
cnt<=cnt+1;
ce<=1'b0;
if(cnt==2'b00)begin
wr<=1'b0;
end
else if(cnt==2'b01)begin
wr<=1'b1;
end
else if(cnt==2'b10)begin
ce<=1'b1;
end
else if(cnt==2'b11)begin
if(addr==17'h1fffe)begin
addr<=17'h0;
cnt<=2'b0;
write_data<=8'h0;
end
else begin
addr<=addr+1;
write_data<=8'h5a;//write_data+1;
ce<=1'b0;
cnt<=2'b0;
end
end
end
read_state:begin
cnt<=cnt+1;
wr<=1'b1;
if(cnt==2'b00)begin
ce<=1'b0;
end
else if(cnt==2'b01)begin
oe<=1'b0;
end
else if(cnt==2'b10)begin
read_data<=dpram_data;
oe<=1'b1;
end
else if(cnt==2'b11)begin
if(addr==17'h1fffe)begin
addr<=17'h0;
cnt<=2'b0;
end
else begin
addr<=addr+1;
//addr<=17'h0;
ce<=1'b1;
cnt<=2'b00;
end
end
end
default:begin
addr<=17'h0;
oe<=1'b1;
ce<=1'b1;
wr<=1'b1;
end
endcase
end
end
assign dpram_ce=ce;
assign dpram_oe=oe;
assign dpram_wr=wr;
assign dpram_addr=addr;
assign dpram_data=(~wr)?write_data:8'hzzzz;
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