M051的SPI的主机FIFO模式使用方法

/**************************************************************************//**

 * [url=home.php?mod=space&uid=288409]@file[/url]     main.c

 * [url=home.php?mod=space&uid=895143]@version[/url]  V3.0

 * $Revision: 2 $

 * $Date: 15/05/22 3:03p $

 * [url=home.php?mod=space&uid=247401]@brief[/url]    Configure SPI0 as Master mode and demonstrate how to communicate

 *           with an off-chip SPI Slave device with FIFO mode. This sample

 *           code needs to work with SPI_SlaveFifoMode sample code.

 *

 * @note

 * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.

 *

 ******************************************************************************/

#include <stdio.h>

#include "M051Series.h"





#define TEST_COUNT 16



uint32_t g_au32SourceData[TEST_COUNT];

uint32_t g_au32DestinationData[TEST_COUNT];

volatile uint32_t g_u32TxDataCount;

volatile uint32_t g_u32RxDataCount;



/* Function prototype declaration */

void SYS_Init(void);

void SPI_Init(void);

extern char GetChar(void);



/* ------------- */

/* Main function */

/* ------------- */

int main(void)

{

    uint32_t u32DataCount;



    /* Unlock protected registers */

    SYS_UnlockReg();

    /* Init System, IP clock and multi-function I/O. */

    SYS_Init();

    /* Lock protected registers */

    SYS_LockReg();



    /* Configure UART0: 115200, 8-bit word, no parity bit, 1 stop bit. */

    UART_Open(UART0, 115200);



    /* Init SPI */

    SPI_Init();



    printf("\n\n");

    printf("+----------------------------------------------------------------------+\n");

    printf("|             SPI Master Mode Sample Code (M05xxDN/DE only)            |\n");

    printf("+----------------------------------------------------------------------+\n");

    printf("\n");

    printf("Configure SPI0 as a master.\n");

    printf("Bit length of a transaction: 32\n");

    printf("The I/O connection for SPI0:\n");

    printf("    SPISS0(P1.4)\n    SPICLK0(P1.7)\n");

    printf("    MISO_0(P1.6)\n    MOSI_0(P1.5)\n\n");

    printf("SPI controller will enable FIFO mode and transfer %d data to a off-chip slave device.\n", TEST_COUNT);

    printf("In the meanwhile the SPI controller will receive %d data from the off-chip slave device.\n", TEST_COUNT);

    printf("After the transfer is done, the %d received data will be printed out.\n", TEST_COUNT);

    printf("The SPI master configuration is ready.\n");



    for(u32DataCount = 0; u32DataCount < TEST_COUNT; u32DataCount++)

    {

        /* Write the initial value to source buffer */

        g_au32SourceData[u32DataCount] = 0x00550000 + u32DataCount;

        /* Clear destination buffer */

        g_au32DestinationData[u32DataCount] = 0;

    }



    printf("Before starting the data transfer, make sure the slave device is ready. Press any key to start the transfer.\n");

    GetChar();

    printf("\n");



    /* Set TX FIFO threshold, enable TX FIFO threshold interrupt and RX FIFO time-out interrupt */

    SPI_EnableFIFO(SPI0, 4, 4);

    SPI_EnableInt(SPI0, SPI_FIFO_TX_INT_MASK | SPI_FIFO_TIMEOUT_INT_MASK);

    

    g_u32TxDataCount = 0;

    g_u32RxDataCount = 0;

    NVIC_EnableIRQ(SPI0_IRQn);



    /* Wait for transfer done */

    while(g_u32RxDataCount < TEST_COUNT);



    /* Print the received data */

    printf("Received data:\n");

    for(u32DataCount = 0; u32DataCount < TEST_COUNT; u32DataCount++)

    {

        printf("%d:\t0x%X\n", u32DataCount, g_au32DestinationData[u32DataCount]);

    }

    /* Disable TX FIFO threshold interrupt and RX FIFO time-out interrupt */

    SPI_DisableInt(SPI0, SPI_FIFO_TX_INT_MASK | SPI_FIFO_TIMEOUT_INT_MASK);

    NVIC_DisableIRQ(SPI0_IRQn);

    printf("The data transfer was done.\n");



    printf("\n\nExit SPI driver sample code.\n");



    /* Reset SPI0 */

    SPI_Close(SPI0);

    while(1);

}



void SYS_Init(void)

{

    /*---------------------------------------------------------------------------------------------------------*/

    /* Init System Clock                                                                                       */

    /*---------------------------------------------------------------------------------------------------------*/

    

    /* Enable external 12MHz XTAL */

    CLK_EnableXtalRC(CLK_PWRCON_XTL12M_EN_Msk);



    /* Waiting for clock ready */

    CLK_WaitClockReady(CLK_CLKSTATUS_XTL12M_STB_Msk);



    /* Switch HCLK clock source to HXT and set HCLK divider to 1 */

    CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_HXT, CLK_CLKDIV_HCLK(1));



    /* Select HXT as the clock source of UART0 */

    CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UART_S_HXT, CLK_CLKDIV_UART(1));



    /* Select HCLK as the clock source of SPI0 */

    CLK_SetModuleClock(SPI0_MODULE, CLK_CLKSEL1_SPI0_S_HCLK, MODULE_NoMsk);



    /* Enable UART peripheral clock */

    CLK_EnableModuleClock(UART0_MODULE);

    /* Enable SPI0 peripheral clock */

    CLK_EnableModuleClock(SPI0_MODULE);



    /* Update System Core Clock */

    /* User can use SystemCoreClockUpdate() to calculate PllClock, SystemCoreClock and CyclesPerUs automatically. */

    SystemCoreClockUpdate();



    /*---------------------------------------------------------------------------------------------------------*/

    /* Init I/O Multi-function                                                                                 */

    /*---------------------------------------------------------------------------------------------------------*/

    /* Set P3 multi-function pins for UART0 RXD and TXD */

    SYS->P3_MFP = SYS_MFP_P30_RXD0 | SYS_MFP_P31_TXD0;



    /* Setup SPI0 multi-function pins */

    SYS->P1_MFP = SYS_MFP_P14_SPISS0 | SYS_MFP_P15_MOSI_0 | SYS_MFP_P16_MISO_0 | SYS_MFP_P17_SPICLK0;

}



void SPI_Init(void)

{

    /*---------------------------------------------------------------------------------------------------------*/

    /* Init SPI                                                                                                */

    /*---------------------------------------------------------------------------------------------------------*/

    /* Configure as a master, clock idle low, 32-bit transaction, drive output on falling clock edge and latch input on rising edge. */

    /* Set IP clock divider. SPI clock rate = 1MHz */

    SPI_Open(SPI0, SPI_MASTER, SPI_MODE_0, 32, 1000000);



    /* Enable the automatic hardware slave select function. Select the SS pin and configure as low-active. */

    SPI_EnableAutoSS(SPI0, SPI_SS, SPI_SS_ACTIVE_LOW);

}



void SPI0_IRQHandler(void)

{

    /* Check RX EMPTY flag */

    while(SPI_GET_RX_FIFO_EMPTY_FLAG(SPI0) == 0)

    {

        /* Read RX FIFO */

        g_au32DestinationData[g_u32RxDataCount++] = SPI_READ_RX0(SPI0);

    }

    /* Check TX FULL flag and TX data count */

    while((SPI_GET_TX_FIFO_FULL_FLAG(SPI0) == 0) && (g_u32TxDataCount < TEST_COUNT))

    {

        /* Write to TX FIFO */

        SPI_WRITE_TX0(SPI0, g_au32SourceData[g_u32TxDataCount++]);

    }

    if(g_u32TxDataCount >= TEST_COUNT)

         SPI_DisableInt(SPI0, SPI_FIFO_TX_INT_MASK); /* Disable TX FIFO threshold interrupt */



    /* Check the RX FIFO time-out interrupt flag */

    if(SPI_GetIntFlag(SPI0, SPI_FIFO_TIMEOUT_INT_MASK))

    {

        /* If RX FIFO is not empty, read RX FIFO. */

        while((SPI0->STATUS & SPI_STATUS_RX_EMPTY_Msk) == 0)

            g_au32DestinationData[g_u32RxDataCount++] = SPI_READ_RX0(SPI0);

    }

}





/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/