IRC16M PLL到32M, 深度睡眠后,变为了16Mhz,PLL32M被关闭

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 楼主| Sam131208 发表于 2025-2-13 16:39 | 显示全部楼层 |阅读模式
PLL, hz, rc, 16
本帖最后由 Sam131208 于 2025-2-17 09:26 编辑

     初始化时,时钟设置为PLL32M, 时钟源为irc16m. 进入了深度睡眠1后唤醒,频率变为了16mhz.     是否还需要其它设置才可以维持PLL设定?

     测试方法为:配置PA8输出系统时钟, 进入深度睡眠1, 唤醒后频率成为16mhz.

      下面是PLL程序:            
  1. static void switch_system_clock_to_32m_irc16m(void)
  2. {
  3.     uint32_t timeout = 0U;
  4.     uint32_t stab_flag = 0U;

  5.     /* select IRC16M as system clock source, deinitialize the RCU */
  6.     rcu_system_clock_source_config(RCU_CKSYSSRC_IRC16M);
  7.     rcu_deinit();

  8.     /* enable IRC16M */
  9.     RCU_CTL |= RCU_CTL_IRC16MEN;

  10.     /* wait until IRC16M is stable or the startup time is longer than IRC16M_STARTUP_TIMEOUT */
  11.     do {
  12.         timeout++;
  13.         stab_flag = (RCU_CTL & RCU_CTL_IRC16MSTB);
  14.     } while((0U == stab_flag) && (IRC16M_STARTUP_TIMEOUT != timeout));

  15.     /* if fail */
  16.     if(0U == (RCU_CTL & RCU_CTL_IRC16MSTB)) {
  17.         while(1) {
  18.         }
  19.     }

  20.     /* set the wait state counter value */
  21.     FMC_WS = (FMC_WS & (~FMC_WS_WSCNT)) | FMC_WAIT_STATE_0;

  22.     /* AHB = SYSCLK */
  23.     RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
  24.     /* APB2 = AHB */
  25.     RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
  26.     /* APB1 = AHB/2 */
  27.     RCU_CFG0 |= RCU_APB1_CKAHB_DIV1;

  28.     /* PLL = (IRC16M/2) * 4 = 32 MHz */
  29.     RCU_CFG1 &= ~(RCU_CFG1_PREDV);
  30.     RCU_CFG1 |= RCU_PLL_PREDV2;
  31.     RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF);
  32.     RCU_CFG0 |= (RCU_PLLSRC_IRC16M | RCU_PLL_MUL4);

  33.     /* enable PLL */
  34.     RCU_CTL |= RCU_CTL_PLLEN;

  35.     /* wait until PLL is stable */
  36.     while(0U == (RCU_CTL & RCU_CTL_PLLSTB)) {
  37.     }

  38.     /* select PLL as system clock */
  39.     RCU_CFG0 &= ~RCU_CFG0_SCS;
  40.     RCU_CFG0 |= RCU_CKSYSSRC_PLL;

  41.     /* wait until PLL is selected as system clock */
  42.     while(0U == (RCU_CFG0 & RCU_SCSS_PLL)) {
  43.     }
  44. }
     附件为测试代码。      如果设置为PLL时钟输出,进入深度睡眠后,时钟输出就停止了。


Deepsleep_wakeup_RTC.zip

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duo点 发表于 2025-2-17 12:06 | 显示全部楼层
重新启用PLL
七毛钱 发表于 2025-2-18 12:00 | 显示全部楼层
更新系统时钟配置
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