用VHDL编写的串口接收程序，有时候会接收不到PC下发的数据，平均100次大概有1次接收不到。process(clk)
begin
if clk'event and clk='1' then
case st1 is
when 0=>if rxd<='0' then
st1<=1;
else
if cont='1' then
--cont=1则清除串口接收的数据
reg<=(others=>'0');
end if;
end if;
when 1=>if cz<8 then
cz<=cz+1;
reg_m(7)<=rxd;
reg_m(6 downto 0)<=reg_m(7 downto 1);
--接收数据并存储
else reg<=reg_m;cz<=(others=>'0');st1<=0;
end if;
when others=>st1<=0;
end case;
end if;
end process; |
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