Protel画PCB最后校验的问题

发表于 2012-12-26 21:58

Processing Rule : Short-Circuit Constraint (Allowed=Not Allowed) (On the board ),(On the board )
Violation between Pad F1-1(4725mil,1340mil)  MultiLayer and
                  Area Fill (4775mil,1265mil) (4875mil,1415mil)  TopLayer
Violation between Pad F1-0(4925mil,1340mil)  MultiLayer and
                  Area Fill (4775mil,1265mil) (4875mil,1415mil)  TopLayer
Violation between Pad F1-2(3725mil,1340mil)  MultiLayer and
                  Area Fill (3775mil,1265mil) (3875mil,1415mil)  TopLayer
Violation between Pad F1-0(3925mil,1340mil)  MultiLayer and
                  Area Fill (3775mil,1265mil) (3875mil,1415mil)  TopLayer
Violation between Pad F1-1(4725mil,1340mil)  MultiLayer and
                  Area Fill (4775mil,1265mil) (4875mil,1415mil)  BottomLayer
Violation between Pad F1-0(4925mil,1340mil)  MultiLayer and
                  Area Fill (4775mil,1265mil) (4875mil,1415mil)  BottomLayer
Violation between Pad F1-2(3725mil,1340mil)  MultiLayer and
                  Area Fill (3775mil,1265mil) (3875mil,1415mil)  BottomLayer
Violation between Pad F1-0(3925mil,1340mil)  MultiLayer and
                  Area Fill (3775mil,1265mil) (3875mil,1415mil)  BottomLayer
Rule Violations :8

Processing Rule : Broken-Net Constraint ( (On the board ) )
Rule Violations :0

Processing Rule : Clearance Constraint (Gap=10mil) (On the board ),(On the board )
Violation between Pad F1-1(4725mil,1340mil)  MultiLayer and
                  Area Fill (4775mil,1265mil) (4875mil,1415mil)  TopLayer
Violation between Pad F1-2(3725mil,1340mil)  MultiLayer and
                  Area Fill (3775mil,1265mil) (3875mil,1415mil)  TopLayer
Violation between Pad F1-1(4725mil,1340mil)  MultiLayer and
                  Area Fill (4775mil,1265mil) (4875mil,1415mil)  BottomLayer
Violation between Pad F1-2(3725mil,1340mil)  MultiLayer and
                  Area Fill (3775mil,1265mil) (3875mil,1415mil)  BottomLayer
Rule Violations :4

Violations Detected : 12
Time Elapsed       : 00:00:04

发表于 2012-12-27 08:18

Short-Circuit Constraint 短路限制
Broken-Net Constraint 断路限制
Clearance Constraint 安全间距限制
下面的那些信息是违反规则的位置信息

发表于 2012-12-27 10:57

你画填充块Fill的时候，没把PAD点和填充块Fill选成同一个net

我估计其中一个是no net

发表于 2012-12-27 11:18

能说的再具体点不？我是初学这个。谢谢啊

发表于 2012-12-27 11:20

SLEET1986 发表于 2012-12-27 08:18
Short-Circuit Constraint 短路限制
Broken-Net Constraint 断路限制
Clearance Constraint 安全间距限制 ...

能说的具体点不？我是初学这个。谢谢！

登录 · 发表于 2012-12-27 12:18

Processing Rule : Short-Circuit Constraint
焊盘与填充不在一个网络

Processing Rule : Clearance Constraint
与上一个是同一区域，因为不在同一网络，所以违反安全间距规则

发表于 2012-12-27 12:39

那要怎么改？谢谢啊

发表于 2012-12-27 12:42

qqmm321 发表于 2012-12-27 12:18
Processing Rule : Short-Circuit Constraint
焊盘与填充不在一个网络

要怎么改？能QQ聊不？我的407076651

发表于 2012-12-27 12:56

:hug:

发表于 2012-12-27 22:47

更改一下填充块的属性,设置NET,网格间距等.

发表于 2012-12-28 15:23

beanandpeach 发表于 2012-12-27 12:56

指点一下啊，谢谢。。。

发表于 2012-12-28 15:25

lark100 发表于 2012-12-27 22:47
更改一下填充块的属性,设置NET,网格间距等.

具体步骤是什么？谢谢啊。。。

发表于 2012-12-28 15:27

heruiling0114 发表于 2012-12-28 15:25
具体步骤是什么？谢谢啊。。。

什么叫填充块？

发表于 2012-12-28 15:38

按快捷键，P,F。FILL就是填充块。双击你的填充块，为它设定NET。你还是网上搜一下设置填充来的利索。百度文库里好多的。

发表于 2012-12-28 15:53

呵呵，谢谢啊！你是干什么的，是不很擅长这个，以后有问题可以请教你不？

发表于 2012-12-28 15:54

wangzeyue 发表于 2012-12-28 15:38
按快捷键，P,F。FILL就是填充块。双击你的填充块，为它设定NET。你还是网上搜一下设置填充来的利索。百度 ...

呵呵，谢谢啊！你是干什么的，是不很擅长这个，以后有问题可以请教你不？

发表于 2012-12-28 21:44

嗨，擅长啥啊。画板子是基本功而已。画多了就会了。

发表于 2013-1-4 16:42

我都是导网络地过去后手动布板的。。。

Protel画PCB最后校验的问题

相关帖子

本帖子中包含更多资源

技术新星奖章

无冕之王奖章

沉静之湖泊

十世金身

技术导师奖章

核心会员奖章

坚毅之洋流

七世轮回

技术领袖奖章

经常做客

技术高手奖章

缘定三生

突出贡献奖章

技术奇才奖章

以坛为家

欢快之小溪

社区建设奖章