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问题描述：<br />在编译某个模块时出现这个问题：<br />Not operational: Clock Skew > Data Delay c3123456:inst|C36:inst1|inst102 c3-123456:inst|C3-6:inst1|inst118 PA14 PA14 None None 1.600 ns<br />Not operational: Clock Skew > Data Delay c3-123456:inst|C3-6:inst1|inst98 c3-123456:inst|C3-6:inst1|inst114 PA14 PA14 None None 3.200 ns<br />Not operational: Clock Skew > Data Delay c3-123456:inst|C3-6:inst1|inst100 c3-123456:inst|C3-6:inst1|inst116 PA14 PA14 None None 3.200 ns<br />Not operational: Clock Skew > Data Delay c3-123456:inst|C3-6:inst1|inst c3-123456:inst|C3-6:inst1|inst112 PA14 PA14 None None 3.200 ns<br />Not operational: Clock Skew > Data Delay c3-123456:inst|C3-6:inst1|inst104 c3-123456:inst|C3-6:inst1|inst120 PA14 PA14 None None 4.000 ns<br />Not operational: Clock Skew > Data Delay c3-123456:inst|C3-6:inst1|inst106 c3-123456:inst|C3-6:inst1|inst122 PA14 PA14 None None 5.600 ns<br />Not operational: Clock Skew > Data Delay c3-123456:inst|C3-6:inst1|inst108 c3-123456:inst|C3-6:inst1|inst124 PA14 PA14 None None 5.600 ns<br />Not operational: Clock Skew > Data Delay c3-123456:inst|C3-6:inst1|inst110 c3-123456:inst|C3-6:inst1|inst126 PA14 PA14 None None 5.600 ns<br />产生如下警告：Warning: Circuit may not operate. Detected 8 non-operational path(s) clocked by clock "PA13" with clock skew larger than data delay. See Compilation Report for details.<br />在帮助文件下查得该警告信息为：<br />CAUSE: The clock skew of the specified number of non-operational path(s), clocked by the specified clock between two registers, is greater than the delay between the same two registers plus the tCO and tSU. As a result, the circuit may not operate. In addition, this warning may appear if either the source register or the destination register is controlled by an inverted undefined clock. When this condition occurs, the Timing Analyzer cannot accurately compute the correct hold relationship without a specified clock requirement. <br /><br />ACTION: View the timing analysis results in the Report window and list the specified paths in the Messages window. If possible, correct the clock skew in the design by using internally registered write/read enables, or by adding LCELL primitives to increase the data path delay. If the warning is related to an undefined, inverted clock, Altera recommends defining the clock by specifying clock settings or by specifying a global default required fMAX before rerunning timing analysis. <br />-----------------------我是分割线------------------<br />看这意思是产生该问题的原因是:这个未操作路径的时钟延迟（该时钟产生于两寄存器之间）比两寄存器之间的延迟+Tco+Tsu的总和还大。还有一个原因可能是两寄存器之中有一个是受未定义的时钟信号（已翻转0、）控制，这种情况下，没有指定的时钟，时序分析器无法准确计算正确的保持关系。<br />上面的ACTION是解决办法，但我只看的懂表面意思但不知道更具体的解释，看的云里雾里的，那位老大能不能就此问题提点下小生啊！或许只几句话就能让我云开雾散，谢谢了！ |
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