|
小弟以前曾学过一点vhdl，时间长差不多忘了，如今为了饭碗问题不得不完成此题，请各位达人赐教，小弟不胜感激。大概意思就是做一个ip地址的分类。<br /><br />This assignment assumes you have basic knowledge of IP (Internet<br />Protocol). If not, please refer to the end of this mail for a quick<br />introduction or see http://en.wikipedia.org/wiki/IPv4 .<br /><br />An IP prefix shows a range of IP addresses that share the same initial<br />portion (e.g. 10.15.20.0/24 shows all the IP addresses in the range from<br />10.15.20.0 to 10.15.20.255)<br /><br />An IP prefix is represented with 5 bytes (4 for the address portion (e.g.<br />to represent 10.15.20.0) and 1 byte for showing the number of shared<br />initial bits (e.g. to represent 24))<br /><br />In this assignment, you will be given 16 nonoverlapping IP ranges<br />represented with IP prefixes.<br /><br />The system has a single clock running at 100 MHz and an asynchronous reset<br />. The system should realize the following two operations.<br /><br /><br />Query Operation:<br />----------------<br /><br />The system receives IP addresses synchoronous to the positive edge of the<br />system clock from its 32-bit input bus INPUT.<br /><br />The system will receive up to one IP address at every clock cycle and you<br />are expected to determine which of the 16 prefixes this address belongs to<br />with minimum delay.<br /><br />For instance, when you receive IP address 10.14.20.4 and if you have a<br />prefix 10.14/16, you need to report this prefix at your output. You can<br />assign a number to each prefix from 0 to 15 and only report this number.<br /><br /><br />Update Operation:<br />-----------------<br /><br />Every 200 ns, a new set of 16 nonoverlapping IP ranges will be given<br />through a separate 8-bit input to replace the current set. This process<br />will be completed in (5 * 16 = 80 clock cycles).<br /><br />During this process an input signal UPDATE will be high. All other times<br />UPDATE signal will be low. When update signal is high, there will be no<br />query operation.<br /><br /><br />Deliverables:<br />------------<br /><br />1. A synthesizable VHDL program of the assignment.<br />2. A testbench VHDL program to thoroughly verify the operation.<br />3. Simulation waveforms to clearly show the system works as specified.<br /> |
|
楼主
