cadence中VCO仿真为啥设置maxsetp=10ps？
2013-8-29 21:57
- EDA 技术
- 10
- 2036
Dead lock only exists in the simulation. In real world, a small purtubation will cause VCO to oscil ...
Who knows how to design analog circuit based on FinFET
2013-8-19 14:22
- EDA 技术
- 0
- 1236
Is there any one who knows how to design analog circuit based on FinFET?
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