求助：Verilog点阵问题

只看该作者 · 2010-9-3 14:56

下面这个程序里，波形仿真中变量f1波形一直是0，大家帮帮忙看看吧~

只看该作者 · 2010-9-3 14:57

module dianzhen(f0,f1,row,line);
input f0;
output f1,line,row;
reg f1;
reg[15:0] row;
reg[15:0] line;
reg j,b;
always @(posedge f0)
         begin
            if(j==2)
               begin
               j<=0;
               f1<=~f1;
               end
               else
               j<=j+1;
         end
always @(posedge f1)
   begin
         if (b>15)
            begin
               b<=0;
            end
      else
            begin
   case(b)
   0:    begin line<=16'b10000000_00000000;row<=16'h0080;end
   1:    begin line<=16'b01000000_00000000;row<=16'h4044;end
   2:    begin line<=16'b00100000_00000000;row<=16'h37FE;end
   3:    begin line<=16'b00010000_00000000;row<=16'h1110;end
   4:    begin line<=16'b00001000_00000000;row<=16'h80A0;end
   5:    begin line<=16'b00000100_00000000;row<=16'h6040;end
   6:    begin line<=16'b00000010_00000000;row<=16'h21B0;end
   7:    begin line<=16'b00000001_00000000;row<=16'h0E0E;end
   8:    begin line<=16'b00000000_10000000;row<=16'h1114;end
   9:    begin line<=16'b00000000_01000000;row<=16'h2110;end
   10:    begin line<=16'b00000000_00100000;row<=16'hE110;end
   11:    begin line<=16'b00000000_00010000;row<=16'h2110;end
   12:    begin line<=16'b00000000_00001000;row<=16'h2110;end
   13:    begin line<=16'b00000000_00000100;row<=16'h2210;end
   14:    begin line<=16'b00000000_00000010;row<=16'h2410;end
   15:    begin line<=16'b00000000_00000001;row<=16'h2010;end
   endcase
   b<=b+1;
            end
   end
endmodule

只看该作者 · 2010-9-3 19:31

always @(posedge f1)

只看该作者 · 2010-9-3 21:10

飘过～

只看该作者 · 2010-9-3 21:58

HEY，原来你在21发帖了啊，大众，猜猜我是谁

3万 · 2010-9-4 11:38

module dianzhen(f0,f1,row,line);
      input f0;
      output f1,line,row;
      reg f1;
      reg[15:0] row;
      reg[15:0] line;
      reg j,b;
      always @(posedge f0)
         begin
            if(j==2)
      ...
大众牌BF 发表于 2010-9-3 14:57