不同外部时钟的初始化
/**
* @brief Xtal initialize
* @param None
* @retval None
*/
en_result_t XtalInit(void)
{
stc_clk_xtal_init_t stcXtalInit;
/* Xtal config */
CLK_XtalStrucInit(&stcXtalInit);
stcXtalInit.u8XtalState = CLK_XTAL_ON;
stcXtalInit.u8XtalDrv = CLK_XTALDRV_LOW;
stcXtalInit.u8XtalMode = CLK_XTALMODE_OSC;
stcXtalInit.u8XtalStb = CLK_XTALSTB_499US;
return CLK_XtalInit(&stcXtalInit);
}
/**
* @brief Xtal32 initialize
* @param None
* @retval None
*/
en_result_t Xtal32Init(void)
{
stc_clk_xtal32_init_t stcXtal32Init;
/* Xtal32 config */
CLK_Xtal32StrucInit(&stcXtal32Init);
stcXtal32Init.u8Xtal32State = CLK_XTAL32_ON;
stcXtal32Init.u8Xtal32Drv = CLK_XTAL32DRV_MID;
stcXtal32Init.u8Xtal32NF = CLK_XTAL32NF_FULL;
return CLK_Xtal32Init(&stcXtal32Init);
}
/**
* @brief PLLH initialize
* @param uPLLM： 分频
uPLLN 备频
uPLLR 分频
uPLLQ 分配
uPLLP 分频
* @retval None
*/
en_result_t PLLHInit(uint16 uPLLM, uint16 uPLLN, uint16 uPLLR, uint16 uPLLQ, uint16 uPLLP)
{
stc_clk_pllh_init_t stcPLLHInit;
/* PCLK0, HCLK Max 240MHz */
/* PCLK1, PCLK4 Max 120MHz */
/* PCLK2, PCLK3 Max 60MHz */
/* EX BUS Max 120MHz */
CLK_ClkDiv(CLK_CATE_ALL, \
(CLK_PCLK0_DIV1 | CLK_PCLK1_DIV2 | CLK_PCLK2_DIV4 | \
CLK_PCLK3_DIV4 | CLK_PCLK4_DIV2 | CLK_EXCLK_DIV2 | \
CLK_HCLK_DIV1));
/* Highspeed SRAM set to 1 Read/Write wait cycle */
SRAM_SetWaitCycle(SRAM_SRAMH, SRAM_WAIT_CYCLE_1, SRAM_WAIT_CYCLE_1);
/* SRAM1_2_3_4_backup set to 2 Read/Write wait cycle */
SRAM_SetWaitCycle((SRAM_SRAM123 | SRAM_SRAM4 | SRAM_SRAMB), SRAM_WAIT_CYCLE_2, SRAM_WAIT_CYCLE_2);
EFM_SetWaitCycle(EFM_WAIT_CYCLE_5);
/* PLLH config */
CLK_PLLHStrucInit(&stcPLLHInit);
/*
8MHz/M*N = 8/1*120/4 =240MHz
*/
stcPLLHInit.u8PLLState = CLK_PLLH_ON;
stcPLLHInit.PLLCFGR = 0UL;
stcPLLHInit.PLLCFGR_f.PLLM = (uPLLM - 1UL);
stcPLLHInit.PLLCFGR_f.PLLN = (uPLLN - 1UL);
stcPLLHInit.PLLCFGR_f.PLLR = (uPLLR - 1UL);//60MHZ
stcPLLHInit.PLLCFGR_f.PLLQ = (uPLLQ - 1UL);
stcPLLHInit.PLLCFGR_f.PLLP = (uPLLP - 1UL);
stcPLLHInit.PLLCFGR_f.PLLSRC = CLK_PLLSRC_XTAL; /* Xtal = 8MHz */
return CLK_PLLHInit(&stcPLLHInit);
}
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