library ieee;
use ieee.std_logic_1164.all;
entity coder is
port(din:in std_logic_vector(0 to 7);
output:out std_logic_vector(0 to 2)):
end coder;
architecture behav of coder is
signal sint:std_logic_vector(4 downto 0);
begin
process(din)
begin
if (din(7)='0') then output<="000";
elsif(din(6)='0') then output<="100";
elsif(din(5)='0') then output<="010";
elsif(din(4)='0') then ouput<="110";
elsif(din(3)='0') then output<="001";
elsif(din(2)='0') then output<="101";
elsif(din(1)='0') then output<="011";
else output<="111";
end if;
end process;
end behav;
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