module v(clk1,in,out1,out2);
input clk1;
input in[3:0];
output [3:0]out1;
output [6:0]out2;
reg [3:0]out1;
reg [6:0]out2;
reg [1:0]t;
always@(negedge clk1)
begin
out1<=4'b0000;
out2<=7'b01111111;
t=t+1;
if(t==2) out1<=4'b1111;
end
always@(in)
begin
if(t==1)begin
case(in)
4'b0000:out2<=7'b1011011;
4'b0001:out2<=7'b1011011;
4'b0010:out2<=7'b1011011;
4'b0011:out2<=7'b1111111;
4'b0100:out2<=7'b1011011;
4'b0101:out2<=7'b1111111;
4'b0110:out2<=7'b1111111;
4'b0111:out2<=7'b0000110;
4'b1000:out2<=7'b1011011;
4'b1001:out2<=7'b1111111;
4'b1010:out2<=7'b1111111;
4'b1011:out2<=7'b0000110;
4'b1100:out2<=7'b1111111;
4'b1101:out2<=7'b0000110;
4'b1110:out2<=7'b0000110;
4'b1111:out2<=7'b0000110;
endcase
end
end
endmodule |
|
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