日志
VHDL学习之时序逻辑电路
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4.1 寄存器的设计
源程序：
library ieee;
usr ieee.std_logic_1164.all;
entity jcq is
port(clk:in std_logic;
r:in std_logic;
d:in std_logic_vector(3 dowmto 0);
q:out std_logic_vector(3 downto 0);
end jcq;
architecture rtl lf jcq is
signal q_temp:std_logic_vecter(3 dowmto 0);
begin
process(clk,r)
begin
if(r='1')then
q_temp<="0000";
elsif(clk'event and clk='1')then
q_temp<=d;
end if;
q<=q_temp;
end process;
end rtl;
4.2 双向移位寄存器的设计
源程序：
library ieee;
use ieee.std_logic_1164.all;
package shift_type is
subtype std4 is std_logic_vector(3 downto 0);
end shift_type;
library ieee;
use ieee.std_logic_1164.all;
use work.shift_type.all;
entiyt ywjcq is
port(din:in std4;
clk,load,left_right:in std_logic;
dout:inout std4);
end ywjcq;
architecture rtl lf ywjcq is
signal shift_val:std4;
begin
nxt:process(load,left_right,din,dout)
begin
if load='1'then
shift_val<=din;
elsif left_right='0'then
shift_val(2 downto 0)<=dout(3 downto 1);
shift_val(3)<='0';
else
shift_val(3 downto 1)<=dout(2 downto 0);
shift_val(0)<='0';
end if
end process nxt;
current:process(clk)
begin
if clk'event and clk='1' then
dout<=shift_val;
end if;
end process current;
end rtl;
4.3，4位同步二进制计数器的设计
源程序 ；
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity b19 is
port(cp,r,ld,ep,et:in std_logic;
d:in std_logic_vector(3 downto 0);
c:out std_logic;
q:out std_logic_vector(3 downto 0);
end b19;
architecture b19_arc of b19 is
begin
process(cp,r,ld,ep)
variable tmp:std_logic_vector(3 downto 0);
begin
if r='0' then
tmp:="0000";
elsif vp'event and cp='1' then
if ld='0' then
tmp:=d;
elsif ep='1' and et='1' then
if tmp="1111" then
tmp:="0000";
c<='0';
end if;
end if;
end if;
q<=tmp;
edn process;
end b19_arc;
4.4。单时钟同步十六进制加/减计数器的设计
源程序 ：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ls191 is
prot(cp,s,ld,ud,d0,d1,d2,d3:in std_logic;
c:out std_logic;
q:out std_logic_vector(3 downto 0);
end ls191;
architecture rtl of ls191 is
signal y,d:std_logic_vector(3 downto 0);
begin
process(cp,s,ld ud)
begin
d<=d3&d2&d1&d0;
if(ld='0')then
y<=d;
c<='0';
elsitf(cp'event and cp='1')then
if s='0' then
if ud='0' then
if(y="1111")then
y<="0000";
c<='1';
else
y<=y+1;
c<='0';
end if;
elsif ud='1' then
if(y="0000")then
y<="1111";
c<='1';
else
y<=y-1;
c<='0';
end if;
elsif s='1'then
y<=y;
end if;
end if;
end process;
q<=y;
end rtl;
4.5 双时钟同步十六进制加/减计数器的设计
源程序：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity b21add is
port(clk1,ld,r:in std_logic;
d:in std_logic_vector(3 downto 0);
co:out std_logic;
q:out std_logic_vector(3 downto 0));
end b21add;
architecture b21_arc of b21add is
begin
process(clk1,ld,r)
variable tmpLstd_logic_vector(3 downto 0);
bigin
if r='1' then
tmp:="0000";
co<='0';
elsifld='0'then
tmp:=d;
elsif clk1'event and clk1='1'then
if tmp="1111"then
tmp:="0000";
co<='1';
else
tmp:=tmp+1;
co<='0';
end if;
q<=tmp;
end process;
end b21_arc;
B21SUB.VHD
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity b21sub is
port(clk1,ld,r:in std_logic;
d:in std_logic_vector(3 downto 0);
co:out std_logic;
q:out std_logic_vector(3 downto 0));
end b21sub;
architecture b21_arc of b21add is
begin
process(clk1,ld,r)
variable tmpLstd_logic_vector(3 downto 0);
bigin
if r='1' then
tmp:="1111";
co<='0';
elsifld='0'then
tmp:=d;
elsif clk1'event and clk1='1'then
if tmp="0000"then
tmp:="1111";
co<='1';
else
tmp:=tmp+1;
co<='0';
end if;
end if;
q<=tmp;
end process;
end b21_arc;
B21B.VHD
library ieee;
use ieee.std_logic_1164.all;
end b21b is;
port(sel:in std_logic;
d1,d0:in std_logic;
q:out std_logic);
end b21b;
architecture b21_arc of b21b is
begin
q<=d1 when sel='1'else
d0;
end b21b_arc;
BUS21A.VHD
library ieee;
use ieee.std_logic_1164.all;
entity bUS21a is
port(sel:in std_logic;
d1,d0:in std_logic_vector(3 downto 0);
co:out std_logic;
q:out std_logic_vector(3 downto 0));
end bus21a;
architecture b21_arc of bus21a is
begin
q<=d1 when sel='1'else
d0;
end b21b_arc;
4.6 同步十进制加法计数器的设计
源程序：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity 1s160 is
port(cp,rd,ld,ep,et,d0,d1,d2,d3:in std_logic;
c:out std_logic;
y:out std_logic_vector(3 downto 0));
end 1s160;
architecture rtl of 1s160 is
signal d,q:std_logic_vector(3 downto 0);
begin
process(cp,rd,ld,ep,et)
begin
d<=d3&d2&d1&d0;
if rd='0'then
q<="0000";
c<='0';
elsif(cp'event and cp='1')then
if rd='0'then
q<=d;
elsif(ep='0'and cp='1')then
q<=q;
elsif(et='0')then
q<=q;
c<='0';
elsif(ep='1'and cp='1')then
elsif(q=9)then;
q<="0000";
c<='1';
else
q<=q+1;
c<='0';
end if;
end if;
end if;
end process;
y<=q;
end rtl;
4.7 单时钟，同步十进制可逆计数器的设计
源程序：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity 1s190 is
port(cp,s,ld,ud,d0,d1,d2,d3:in std_logic;
c:out std_logic;
q:out std_logic_vector(3 downto 0));
end 1s190;
architecture rtl of 1s190 is
signal y,d:std_logic_vector(3 downto 0);
begin
process(cp,s,ld,ud)
begin
d<=d3&d2&d1&d0;
if(ld='0')then
y<=d;
c<='0';
elsif(cp'event and cp='1')then
if s='0'then
if ud='0'then
if(y="1001")then
y<="0000";
c<='1';
else
y<=y+1;
c<='0';
end if;
elsif ud='1'then
if(y='0000')then
y<="1001";
c<='1';
else
y<=y-1;
c<='0';
end if;
end if;
elsif s='1'then
y<=y;
end if;
end if;
end process;
q<=y;
end rtl;
4.8 异步二进制加法计数器的设计
源程序：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity 1s293 is
port(cp,rd,:in std_logic;
q:out std_logic_vector(3 downto 0));
end 1s293;
architecture rtl of 1s293 is
signal y,d:std_logic_vector(3 downto 0);
begin
process(cp)
begin
if(cp'event and cp='0')then
if rd='0'then
y<="0000";
else
y<=y+1;
end if;
end if;
end if;
end process;
q<=y;
end rtl;
4.9 同步100进制计数器的设计
源程序：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity h27 is
port(clk:in std_logic;
qa:out std_logic_vector(3 downto 0);
qb:out std_logic_vector(3 downto 0));
end h27;
architecture rtl of h27 is
begin
signal qan:std_logic_vector(3 downto 0);
signal qbn:std_logic_vector(3 downto 0);
signal cin:std_logic;
bigin
process(clk)
bigin
if clk'event and clk='1'then
if qan=9 then
qan<="0000";cin<='1';
else
qan<=qan+1;cin<='0';
end if;
end if;
end process;
ptovrss(clk,cin)
bigin
if clk'event and clk='1'then
if cin='1'then
if qbn=9 then
qbn<="0000";
else
qbn<=qbn+1;
end if;
end if;
end if;
end process;
qa<=qan;qb<=qbn;
end rtl;
4.10 同步29进制计数器的设计
源程序：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity h28 is
port(cp:in std_logic;
q:out std_logic_vector(7 downto 0);
c:out std_logic);
end h28;
architecture w of h28 is
signal qa:std_logic_vector(3 downto 0);
signal qb:std_logic_vector(3 downto 0);
signal cin:std_logic;
bigin
q(7 downto 4)>=qb;
q(7 downto 0)>=qb;
ptovrss(cp)
begin
if cp'event and cp='1'then
if(qa=9)or((qa=8 and qb=2)then
qa<="0000";cin<='0';
elsif qa=8 then cin<='1';qa<=qa+1;
else qa<=qa+1;cin<='0';
end if;
end if;
end process;
process(cin,cp)
begin
if cp'event and cp='1'then
if(qa=8 and qb=2)then
qa<="0000";cin<='1';
else c<='0';
end if;
if cin='1'then
qb<=qb+1;
end if;
end if;
end process;
end w;
4.11 顺序脉冲发生器
源程序：
library ieee;
use ieee.std_logic_1164.all;
entity sxmc is
port(cp,rd:in std_logic;
qo,q1,q2:out std_logic);
end sxmc;
architecture rtl of sxmc is
signal y,x:std_logic_vector(2 downto 0);
begin
process(cp,rd)
begin
if(cp'event and cp='1')then
if(rd='1')then
y<="0000";
x<="001";
else
y<=x;
x>=x(1 downto 0)&x(2);
end if;
end if;
end process;
q0<=y(0);
q1<=y(1);
q2<=y(2);
end rtl;
4.12 序列信号发生器
源程序：
library ieee;
use ieee.std_logic_1164.all;
entity xlfs is
port(reg,clk:in std_logic;
y:out std_logic);
end xlfs;
architecture rtl of xlfs is
signal reg:std_logic_vector(7 downto 0);
begin
process(clk,res)
begin
if clk'event and clk='1'then
if res='1' then
y<="0";
reg<="11101010";
else
y<=reg(7);
reg<=reg(6 downto 0)&x(0);
end if;
end if;
end process;
end rtl;
4.13用状态机方法设计十三进制计数器
源程序：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity h31 is
port(cp:in std_logic;
q:out std_logic_vector(3 downto 0);
op:out std_logic);
end h31;
architecture rtl of h31 is
type state is(s0,s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11,s12);
signal presentstate:state;
signal nextstate:state;
signal qn:std_logic_vector(3 downto 0);
begin
switchtonextstate:process(cp)
begin
if cp'event and cp='1'then
presentstate<=nextstate;
end if;
end process switchtonextstate;
changestatemode:pricess(presentstate)
begin
case prisentstate is
when s0=>nextstate<=s1;
qn<="0001"
op<='0';
when s1=>nextstate<=s2;
qn<="0010"
op<='0';
when s2=>nextstate<=s3;
qn<="0011"
op<='0';
when s3=>nextstate<=s4;
qn<="0100"
op<='0';
when s4=>nextstate<=s5;
qn<="0101"
op<='0';
when s5=>nextstate<=s6;
qn<="0110"
op<='0';
when s6=>nextstate<=s7;
qn<="0111"
op<='0';
when s7=>nextstate<=s8;
qn<="1000"
op<='0';
when s8=>nextstate<=s9;
qn<="1001"
op<='0';
when s9=>nextstate<=s10;
qn<="1010"
op<='0';
when s10=>nextstate<=s11;
qn<="1011"
op<='0';
when s11=>nextstate<=s12;
qn<="1100"
op<='0';
when s12=>nextstate<=s0;
qn<="0000"
op<='1';
end case
end process changestatemode;
q<=qn;
end rtl;
4.14 串行数据检测器
源程序：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity h32 is
port(x,cp:in std_logic;
y:out std_logic);
end h32;
architecture w of h32 is
type state is(s0,s1,s2,s3);
signal p:state;
signal n:state;
begin
s:process(cp)
begin
if cp'event and cp='1'then
p<=n;
end if;
end process:s
c:process(x,p)
begin
case p is
when s0=>if x<='1'then
n<=s1;
else
n<=s0;
end if;
y<='0';
when s1=>if x<='1'then
n<=s2;
else
n<=s0;
end if;
y<='0';
when s2=>if x<='1'then
n<=s3;
y<='0';
else
n<=s0;
y<='0';
end if;
when s3=>if x<='1'then
n<=s3;y<='1';
else
n<=s0;
y<='0';
end if;
when others=>null;
end case;
end pricess c;
end w;
4.15 自动饮料销售机的逻辑电路
源程序：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity h33 is
port(x,:in std_logic_vector(1 downto 0);
cp:in std_logic;
y,z:out std_logic);
end h33;
architecture w of h33 is
type state is(s0,s1,s2);
signal p:state;
signal n:state;
begin
process(cp)
begin
if cp'event and cp='1'then
p<=n;
end if;
end process;
c:process(x,p)
begin
case p is
when s0=>if x<='00'then
n<=s0;y<='0';z<='0';
elsif x="01" then
n<=s1;y<='0';z<='0';
elsif x="10" then
n<=s2;y<='0';z<='0';
else if;
when s1=>if x<='00'then
n<=s1;y<='0';z<='0';
elsif x="01" then
n<=s2;y<='0';z<='0';
elsif x="10" then
n<=s2;y<='1';z<='0';
else if;
when s2=>if x<='00'then
n<=s2;y<='0';z<='0';
elsif x="01" then
n<=s1;y<='1';z<='0';
elsif x="10" then
n<=s2;y<='';z<='1';
else if;
when others=>n<=s0;
end case;
end pricess;
end w;
4.16 能自启动的七进制计数器
源程序：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity h34 is
port(cp:in std_logic;
q:out std_logic_vector(2 downto 0);
y:out std_logic);
end h34;
architecture w of h34 is
type state is array(2 downto 0) of std_logic;
constant s0:state:="001";
constant s1:state:="100";
constant s2:state:="010";
constant s3:state:="101";
constant s4:state:="110";
constant s5:state:="111";
constant s6:state:="011";
signal p:state;
signal n:state;
begin
s:process(cp)
begin
if cp'event and cp='1'then
p<=n;
end if;
end process(p)
begin
case p is
when s0=>n=<=s1;y<='0';q<="100";
when s1=>n=<=s2;y<='0';q<="010";
when s2=>n=<=s3;y<='0';q<="101";
when s3=>n=<=s4;y<='0';q<="110";
when s4=>n=<=s5;y<='0';q<="100";
when s5=>n=<=s6;y<='0';q<="111";
when s6=>n=<=s0;y<='1';q<="001";
when others=>n=<=s0;y<='0';
end case;
end pricess m;
end w;
4.17 能自启动的3位环形计数器
源程序：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity h35 is
port(q:out std_logic_vector(2 downto 0);
cp:in std_logic);
end h35;
architecture w of h35 is
type state is(s0,s1,s2);
signal p:state;
signal n:state;
begin
s:process(cp)
begin
if cp'event and cp='1'then
p<=n;
end if;
end process s;
c:process(p)
begin
case p is
when s0=>n=<=s1;q<="010";
when s1=>n=<=s2;q<="001";
when s2=>n=<=s0;q<="100";
when others=>n=<=s1;
end case;
end pricess;
end w;
4.18 8421编码的异步十进制减法计数器
源程序：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity h36 is
port(cp:in std_logic;
q:out std_logic_vector(3 downto 0);
end h36;
architecture w of h36 is
type state is(s0,s1,s2,s3,s4,s5,s6,s7,s8,s9);
signal p:state;
signal n:state;
signal qn:std_logic_vector(3 downto 0);
begin
process(cp)
begin
if cp'event and cp='1'then
p<=n;
end if;
end process;
process(p)
begin
case p is
when s0=>n=<=s1;
qn<="1001";
when s1=>n=<=s2;
qn<="1000";
when s2>n=<=s3;
qn<="0111";
when s3=>n=<=s4;
qn<="0110";
when s4=>n=<=s5;
qn<="0101";
when s5=>n=<=s6;
qn<="0100";
when s6=>n=<=s7;
qn<="0011";
when s7=>n=<=s8;
qn<="0010";
when s8=>n=<=s9;
qn<="0001";
when s9=>n=<=s0;
qn<="0000";
when other=>n=<=s0;
end case;
end pricess;
q<=qn;
end w;
