FUNDAMENTALS OF SEMICONDUCTOR C-V MEASUREMENTS

Lee Stauffer
Keithley Instruments, Inc.

Deck: C-V measurements provide a wealth of information about device and material characteristics.

A Universal Test
Capacitance-voltage (C-V) testing is widely used to determine semiconductor parameters, particularly in MOSCAP and MOSFET structures. However, other types of semiconductor devices and technologies can also be characterized with C-V measurements, including bipolar junction transistors (BJTs), JFETs, III-V compound devices, photovoltaic cells, MEMs devices, organic TFT displays, photodiodes, carbon nanotubes (CNTs), and many others.

The fundamental nature of these measurements makes them useful in a wide range of applications and disciplines. They are used in the research labs of universities and semiconductor manufacturers to evaluate new materials, processes, devices, and circuits. C-V measurements are extremely important to product and yield enhancement engineers, who are responsible for improving processes and device performance. Reliability engineers use these measurements to qualify material suppliers, monitor process parameters, and analyze failure mechanisms.

With appropriate methodologies, instrumentation, and software, a multitude of semiconductor device and material parameters can be derived. This information is used all along the production chain beginning with evaluation of epitaxially grown crystals, including parameters such as average doping concentration, doping profiles, and carrier lifetimes. In wafer processes, C-V measurements can reveal oxide thickness, oxide charges, mobile ions (contamination), and interface trap density. These measurements continue to be used after other process steps, such as lithography, etching, cleaning, dielectric and polysilicon depositions, and llization. After devices are fully fabricated on the wafer, C-V is used to characterize threshold voltages and other parameters during reliability and basic device testing and to model the performance of these devices.

The Physics of Semiconductor Capacitance
A MOSCAP structure is a fundamental device formed during semiconductor fabrication (see Figure 1). Although these devices may be used in actual circuits, they are typically integrated into fabrication processes as a test structure. Since they are simple structures and their fabrication is easy to control, they are a convenient way to evaluate the underlying processes.

Figure 1. C-V measurement circuit for a MOSCAP structure formed on a P-type substrate.

The l/polysilicon layer shown in Figure 1 is one plate of the capacitor, and silicon dioxide is the insulator. Since the substrate below the insulating layer is a semiconducting material, it is not by itself the other plate of the capacitor. In effect, the majority charge carriers become the other plate. Physically, capacitance, C, is determined from the variables in the following equation:

C = A (κ/d), where
A is the area of the capacitor,
κ is the dielectric constant of the insulator, and
d is the separation of the two plates.
Therefore, the larger A and κ are, and the thinner the insulator is, the higher the capacitance will be. Typically, semiconductor capacitance values range from nanofarads to picofarads, or smaller.

The procedure for taking C-V measurements involves the application of DC bias voltages across the capacitor while making the measurements with an AC signal (Figure 1). Commonly, AC frequencies from about 10kHz to 10MHz are used for these measurements. The bias is applied as a DC voltage sweep that drives the MOSCAP structure from its accumulation region into the depletion region, and then into inversion (Figure 2).

Figure 2. DC bias sweep of MOSCAP structure obtained during C-V testing.

A strong DC bias causes majority carriers in the substrate to accumulate near the insulator interface. Since they can’t get through the insulating layer, capacitance is at a maximum in the accumulation region as the charges stack up near that interface (i.e., d is at a minimum). See Figure 1. One of the fundamental parameters that can be derived from C-V accumulation measurements is the silicon dioxide thickness, tox.

As bias voltage is decreased, majority carriers get pushed away from the oxide interface and the depletion region forms. When the bias voltage is reversed, charge carriers move the greatest distance from the oxide layer, and capacitance is at a minimum (i.e., d is at a maximum). From this inversion region capacitance, the number of majority carriers can be derived. The same basic concepts apply to MOSFET transistors, even though their physical structure and doping is more complex.

Many other parameters can be derived from the three regions shown in Figure 2 as the bias voltage is swept through them. Different AC signal frequencies can reveal additional details. Low frequencies reveal what are called quasistatic characteristics, whereas high frequency testing is more indicative of dynamic performance. Both types of C-V testing are often required.

Basic Test Setup
Figure 3 is the block diagram of a basic C-V measurement setup. Because C-V measurements are actually made at AC frequencies, the capacitance for the device under test (DUT) is calculated with the following:
CDUT = IDUT / 2πfVac, where
IDUT is the magnitude of the AC current through the DUT,
f is the test frequency, and
Vac is the magnitude and phase angle of the measured AC voltage
In other words, the test measures the AC impedance of the DUT by applying an AC voltage and measuring the resulting AC current, AC voltage, and impedance phase angle between them.

Figure 3. Basic test setup for C-V measurements.

These measurements take into account series and parallel resistance associated with the capacitance, as well as the dissipation factor (leakage). Figure 4 illustrates the basic circuit variables that can be derived from the measurements.

Figure 4. Basic electrical variables available from C-V measurements