是布线完了再看吗?<br />Compile report:<br />===============<br /><br /> CORE Used: 5137 Total: 13824 (37.16%)<br /> IO (W/ clocks) Used: 18 Total: 119 (15.13%)<br /> Differential IO Used: 0 Total: 58 (0.00%)<br /> GLOBAL (Chip+Quadrant) Used: 1 Total: 18 (5.56%)<br /> PLL Used: 1 Total: 2 (50.00%)<br /> RAM/FIFO Used: 1 Total: 24 (4.17%)<br /> Low Static ICC Used: 0 Total: 1 (0.00%)<br /> FlashROM Used: 0 Total: 1 (0.00%)<br /> User JTAG Used: 0 Total: 1 (0.00%)<br /> RC oscillator Used: 0 Total: 1 (0.00%)<br /> XTL oscillator Used: 0 Total: 1 (0.00%)<br /> NVM Used: 1 Total: 2 (50.00%)<br /> AB Used: 0 Total: 1 (0.00%)<br /> AnalogIO Used: 0 Total: 46 (0.00%)<br /> VRPSM Used: 0 Total: 1 (0.00%)<br /> No-Glitch MUX Used: 0 Total: 2 (0.00%)<br /><br />Global Information:<br /><br /> Type | Used | Total<br /> ----------------|--------|-------------<br /> Chip global | 1 | 6 (16.67%)<br /> Quadrant global | 0 | 12 (0.00%)<br /><br />Core Information:<br /><br /> Type | Instances | Core tiles<br /> --------|--------------|-----------<br /> COMB | 4271 | 4271<br /> SEQ | 570 | 866<br /><br />I/O Function:<br /><br /> Type | w/o register | w/ register | w/ DDR register<br /> ------------------------------|---------------|--------------|----------------<br /> Input I/O | 2 | 0 | 0<br /> Output I/O | 16 | 0 | 0<br /> Bidirectional I/O | 0 | 0 | 0<br /> Differential Input I/O Pairs | 0 | 0 | 0<br /> Differential Output I/O Pairs | 0 | 0 | 0<br /><br />I/O Technology:<br /><br /> | Voltages | I/Os<br /> --------------------------------|-------|-------|-------|--------|--------------<br /> I/O Standard(s) | Vcci | Vref | Input | Output | Bidirectional<br /> --------------------------------|-------|-------|-------|--------|--------------<br /> LVTTL | 3.30v | N/A | 2 | 16 | 0<br /><br />Net information report:<br />=======================<br /><br />The following nets drive enable flip-flops that have been remapped to a 2-tile implementation:<br /> EffCnt Type Name<br /> --------------------------<br /> 12 SET/RESET_NET Net : U3/MXXXXXXXXXXXXXXXXXXXX10<br /> Driver: U3/MXXXXXXXXXXXXXXXPMXXXXXXXXXXXXXX6<br /> 12 SET/RESET_NET Net : U3/MXXXXXXXXXXXXXXXXXXXX9<br /> Driver: U3/MXXXXXXXXXXXXXXXPMXXXXXXXXXXXXXX5<br /> 12 SET/RESET_NET Net : U3/MXXXXXXXXXXXXXXXXXXXX7<br /> Driver: U3/MXXXXXXXXXXXXXXXPMXXXXXXXXXXXXXX3<br /> 12 SET/RESET_NET Net : U3/MXXXXXXXXXXXXXXXXXXXXX38<br /> Driver: U3/MXXXXXXXXXXXXXXXPMXXXXXXXXXXXXXXX29<br /> 12 SET/RESET_NET Net : U3/MXXXXXXXXXXXXXXXXXXXXX37<br /> Driver: U3/MXXXXXXXXXXXXXXXPMXXXXXXXXXXXXXXX28<br /> 12 SET/RESET_NET Net : U3/MXXXXXXXXXXXXXXXXXXXXX48<br /> Driver: U3/MXXXXXXXXXXXXXXXPMXXXXXXXXXXXXXXX23<br /> 12 SET/RESET_NET Net : U3/MXXXXXXXXXXXXXXXXXXXXX52<br /> Driver: U3/MXXXXXXXXXXXXXXXPMXXXXXXXXXXXXXXX17<br /> 12 SET/RESET_NET Net : U3/MXXXXXXXXXXXXXXXXXXXXX53<br /> Driver: U3/MXXXXXXXXXXXXXXXPMXXXXXXXXXXXXXXX16<br /> 11 SET/RESET_NET Net : U3/MXXXXXXXXXXXXXXXXXXXXX35<br /> Driver: U3/MXXXXXXXXXXXXXXXPMXXXXXXXXXXXXXXX32<br /> 11 SET/RESET_NET Net : U3/MXXXXXXXXXXXXXXXXXXXXXX2<br /> Driver: U3/MXXXXXXXXXXXXXXXPMXXXXXXXXXXXXXXXX<br /><br />The following nets have been assigned to a chip global resource:<br /> Fanout Type Name<br /> --------------------------<br /> 570 CLK_NET Net : mcuclk<br /> Driver: U0/Core<br /> Source: ESSENTIAL<br /><br />High fanout nets in the post compile netlist:<br /> Fanout Type Name<br /> --------------------------<br /> 13 INT_NET Net : U3/MXXXXXXXXXXXXXXXXXXXXX4<br /> Driver: U3/XXXYXXXXXX/MXXXXXXXXXXXXXXXXPXXXXXXXXXX0<br /> 13 INT_NET Net : U3/MXXXXXXXXXXXXXXXXXXXXXXX5<br /> Driver: U3/XXXYXXXXXX/MXXXXXXXXXXXXXXXXPXXXXXXXXXXXX1<br /> 13 INT_NET Net : U3/MXXXXXXXXXXXXXXXXPXXXXXXXX<br /> Driver: U3/XXXYXXXXXX0/MXXXXXXXXXXXXXXXXXXXXPXXXX2<br /> 13 INT_NET Net : U3/XFXXXXXXXXXX2<br /> Driver: U3/XXXYXXXXXX3/MXXXXXXXXXXXXXXXXXMXFXXXXLXXXMXFXXXXXXXXXX9<br /> 13 INT_NET Net : U3/MXXXXXXXXXXXXXXFXXXXXXXXXX7<br /> Driver: U3/XXXYXXXXXX3/MXXXXXXXXXXXXXXXXXMXFXXXXLXXXMXFXXXXXXXXXX8<br /> 13 INT_NET Net : U3/MXXXXXXXXXXXXXXFXXXXXXXXXX4<br /> Driver: U3/XXXYXXXXXX3/MXXXXXXXXXXXXXXXXXMXFXXXXLXXXMXFXXXXXXXXXX7<br /> 13 INT_NET Net : U3/MXXXXXXXXXXXXXXFXXXXXXXXXX<br /> Driver: U3/XXXYXXXXXX3/MXXXXXXXXXXXXXXXXXMXFXXXXLXXXMXFXXXXXXXXXX6<br /> 13 INT_NET Net : U3/MXXXXXXXXXXXXXXFXXXXXXXXXX1<br /> Driver: U3/XXXYXXXXXX3/MXXXXXXXXXXXXXXXXXMXFXXXXLXXXMXFXXXXXXXXXX10<br /> 13 INT_NET Net : U3/XXXYXXXXXX4/MXXXXXXXXXXXXXXXMXMXXXLXXPXXXXXX3<br /> Driver: U3/XXXYXXXXXX4/MXXXXXXXXXXXXXXXMXMXXXLXXPXXXXXXXXXXX1<br /> 13 INT_NET Net : U3/XXXYXXXXXX4/MXXXXXXXXXXXXXXXMXMXXXLXXPXXXX4<br /> Driver: U3/XXXYXXXXXX4/MXXXXXXXXXXXXXXXMXMXXXLXXPXXXXXXXXX5<br /><br />Nets that are candidates for clock assignment and the resulting fanout:<br /> Fanout Type Name<br /> --------------------------<br /> 563 SET/RESET_NET Net : U3/MXXXXXXXXXXXXXXXPMXXXXXXXXXXXX<br /> Driver: U3/MXXXXXXXXXXXXXXXPMXXXXXXXXXXXX<br /> 47 INT_NET Net : memdatai[6]<br /> Driver: U1/NVM_INST<br /> 40 INT_NET Net : memdatai[5]<br /> Driver: U1/NVM_INST<br /> 40 INT_NET Net : memdatai[7]<br /> Driver: U1/NVM_INST<br /> 39 INT_NET Net : memdatai[2]<br /> Driver: U1/NVM_INST<br /> 38 INT_NET Net : memdatai[4]<br /> Driver: U1/NVM_INST<br /> 37 INT_NET Net : memdatai[3]<br /> Driver: U1/NVM_INST<br /> 32 INT_NET Net : memdatai[1]<br /> Driver: U1/NVM_INST<br /> 31 INT_NET Net : memdatai[0]<br /> Driver: U1/NVM_INST<br /> 22 INT_NET Net : mempsacki<br /> Driver: U2/mempsacki<br /><br />The Compile command succeeded ( 00:00:30 )<br />
|