直接设寄存器:
OSC_CR1 This register selects the divider value for variable clocks 1 and 2 (VC1 and VC2).
7:4 VC1 Divider[3:0] Internal Main Oscillator External Clock 0h 24 MHz EXTCLK / 1 1h 12 MHz EXTCLK / 2 2h 8 MHz EXTCLK / 3 3h 6 MHz EXTCLK / 4 4h 4.8 MHz EXTCLK / 5 5h 4 MHz EXTCLK / 6 6h 3.43 MHz EXTCLK / 7 7h 3 MHz EXTCLK / 8 8h 2.67 MHz EXTCLK / 9 9h 2.40 MHz EXTCLK / 10 Ah 2.18 MHz EXTCLK / 11 Bh 2.00 MHz EXTCLK / 12 Ch 1.85 MHz EXTCLK / 13 Dh 1.71 MHz EXTCLK / 14 Eh 1.6 MHz EXTCLK / 15 Fh 1.5 MHz EXTCLK / 16 3:0 VC2 Divider[3:0] Internal Main Oscillator External Clock 0h (24 / (OSC_CR1[7:4]+1)) / 1 (EXTCLK / (OSC_CR1[7:4]+1)) / 1 1h (24 / (OSC_CR1[7:4]+1)) / 2 (EXTCLK / (OSC_CR1[7:4]+1)) / 2 2h (24 / (OSC_CR1[7:4]+1)) / 3 (EXTCLK / (OSC_CR1[7:4]+1)) / 3 3h (24 / (OSC_CR1[7:4]+1)) / 4 (EXTCLK / (OSC_CR1[7:4]+1)) / 4 4h (24 / (OSC_CR1[7:4]+1)) / 5 (EXTCLK / (OSC_CR1[7:4]+1)) / 5 5h (24 / (OSC_CR1[7:4]+1)) / 6 (EXTCLK / (OSC_CR1[7:4]+1)) / 6 6h (24 / (OSC_CR1[7:4]+1)) / 7 (EXTCLK / (OSC_CR1[7:4]+1)) / 7 7h (24 / (OSC_CR1[7:4]+1)) / 8 (EXTCLK / (OSC_CR1[7:4]+1)) / 8 8h (24 / (OSC_CR1[7:4]+1)) / 9 (EXTCLK / (OSC_CR1[7:4]+1)) / 9 9h (24 / (OSC_CR1[7:4]+1)) / 10 (EXTCLK / (OSC_CR1[7:4]+1)) / 10 Ah (24 / (OSC_CR1[7:4]+1)) / 11 (EXTCLK / (OSC_CR1[7:4]+1)) / 11 Bh (24 / (OSC_CR1[7:4]+1)) / 12 (EXTCLK / (OSC_CR1[7:4]+1)) / 12 Ch (24 / (OSC_CR1[7:4]+1)) / 13 (EXTCLK / (OSC_CR1[7:4]+1)) / 13 Dh (24 / (OSC_CR1[7:4]+1)) / 14 (EXTCLK / (OSC_CR1[7:4]+1)) / 14 Eh (24 / (OSC_CR1[7:4]+1)) / 15 (EXTCLK / (OSC_CR1[7:4]+1)) / 15 Fh (24 / (OSC_CR1[7:4]+1)) / 16 (EXTCLK / (OSC_CR1[7:4]+1)) / 16
OSC_CR3:
7:0 VC3 Divider[7:0] Refer to the OSC_CR4 register. 00h Input Clock 01h Input Clock / 2 02h Input Clock / 3 03h Input Clock / 4 ... ... FCh Input Clock / 253 FDh Input Clock / 254 FEh Input Clock / 255 FFh Input Clock / 256
|