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自己刚开始学习VHDL和Quartus II 7.2，写了下面一段程序后编译总是出错，希望高手指点一下，在下先谢谢了！<br /><br />程序如下：<br />library ieee;<br />use ieee.std_logic_1164.all;<br />use ieee.std_logic_unsigned.all;<br />entity adder is<br /> port(a1: in bit_vector;<br /> a2: in bit_vector;<br /> cnt1: in bit;<br /> pout: out bit_vector);<br /> end adder;<br />architecture func of adder is<br />begin <br /> cale:process(cnt1)<br /> begin<br /> if(cnt1='1')then pout <= a1 + a2;<br /> end if;<br /> end process;<br />end func;<br /><br />其实就是一个很简单的加法器，可是编译不通过，显示错误信息如下：<br /><br />Error (10327): VHDL error at adder.vhd(14): can't determine definition of operator ""+"" -- found 0 possible definitions<br /><br />希望高手帮忙解答！！！<br />谢谢！ |
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