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Table 7: Bit rate afjustment factor D<br /> -------<br /><br /> -------------------------------------------------------<br /> DI | 0000 0001 0010 0011 0100 0101 0110 0111<br /> ------+------------------------------------------------<br /> D | RFU 1 2 4 8 16 RFU RFU<br /> -------------------------------------------------------<br /><br /> -------------------------------------------------------<br /> DI | 1000 1001 1010 1011 1100 1101 1110 1111<br /> ------+------------------------------------------------<br /> D | RFU RFU 1/2 1/4 1/8 1/16 1/32 1/64<br /> -------------------------------------------------------<br /> RFU : Reserved for Future Use<br /><br /><br /> - Programming voltage factor P<br /> ----------------------------<br /><br /> PI1 from 5 to 25 gives the value of P in volts. PI1=0 indicates that VPP<br /> is connected in the card which generates an internal programming voltage<br /> from VCC. Other values of PI1 are reserved for future use.<br /><br /> When PI2 is present, the indication of PI1 should be ignores. PI2 from<br /> 50 to 250 gives the value of P in 0.1V. Other values of PI2 are reserved<br /> for future use.<br /><br /><br /> Table 8 : Maximum programming current factor I<br /> -------<br /> -------------------------------<br /> II | 00 01 10 11<br /> -----+-------------------------<br /> I | 25 50 100 RFU<br /> -------------------------------<br /><br /> - Extra guardtime N<br /> -----------------<br /><br /> N codes directly the extra guard time, from 0 to 254 etu. N=255<br /> indicates that the minimum delay between the start edges of two<br /> consecutives characters is reduced to 11 etu.<br /><br /><br /> b - Answer to Reset in synchronous transmission<br /> -------------------------------------------<br /> * Clock frequency and bit rate<br /> """"""""""""""""""""""""""""<br /> There is a linear relationship between the bit rate on the I/O line and<br /> the clock frequency provided by the clock interface device on CLK.<br /><br /> Any clock frequency between 7kHz and 50kHz may be chosen for the reset<br /> sequence. A clock frequency of 7kHz corresponds to 7kbit/s, and values<br /> of the clock frequency up to 50kHz cause corresponding bit rates to be<br /> transmitted.<br /><br /> * Structure of the header of the Answer to Reset<br /> """"""""""""""""""""""""""""""""""""""""""""""<br /> The reset operation results in an answer from the card containing a<br /> header transmitted from the card to the interface. The header has a<br /> fixed length of 32 bits and begins with two mandatory fields of 8 bits,<br /> H1 and H2.<br /><br /> The chronological order of transmission of information bits shall<br /> correcpond to bit identification b1 to b32 with the least significant<br /> bit transmitted first. The numerical meaning corresponding to each<br /> information bit considered in isolation is that of the digit.<br /><br /> - 0 for a unit corresponding to state A (space)<br /> - 1 for a unit corresponding to state Z (mark)<br /><br /> * Timing of the haeder<br /> """"""""""""""""""""<br /> After the reset procedure, the output information is controlled by clock<br /> pulses. The first clock pulse is applied between 10us and 100us (t14)<br /> after the falling edge on RST to read the data bits from the card. State<br /> H of the clock pulses can be varied between 10us and 50us (t15) and<br /> state L between 10us and 100us (t16).<br /><br /> The first data bit is obtained on I/O while the clock is low and is<br /> valid 10us (t13) at least after the falling edge on RST. The following<br /> data bits are valid 10us (t17) at least after the falling edge on CLK.<br /> Each data bit is valid until the next falling edge the following clock<br /> pulse on CLK. The data bits can therefore be sampled at the rising edge<br /> of the following clock pulses.<br /><br /> * Data content of the header<br /> """"""""""""""""""""""""""<br /> The header allows a quick determination of whelther the card and the<br /> interface device are compatible. If there is no compatibility, the<br /> contacts shall be desactivated.<br /><br /> The first field H1 codes the protocol type. The values of the codes and<br /> the corresponding protocol type are<br /><br /> Hexadecimal value protocol type<br /> -----------------------------------<br /> 00 and ff not to be used<br /> 01 to FE each value is assigned<br /> by ISO/IEC JTC1/SC17 to<br /> one protocol type<br /><br /> The second field H2 codes parameters for the protocol type coded in<br /> field H1. The values of H2 are to be assigned by ISO/IEC JTC1/SC17.<br /><br /><br /> 2.3.5) Protocol type selection (PTS)<br /> -----------------------------<br /> If only one protocol type and FI=D=1 (default value of TA1) and N smaller<br /> than 255 is indicated in the answer to reset. The transmission protocol<br /> associated to the protocol type may be started immediately after the<br /> transmission of answer to reset.<br /><br /> If more than one protocol type and/or TA1 parameter values other than the<br /> default values and/or N equeal to 255 is/are indicated in the answer to<br /> reset, the card shall know unambiguously, after having sent the answer to<br /> reset, which protocol type or/and transmission parameter values (FI, D, N)<br /> will be used. Consequently a selection of the protocol type and/or the<br /> transmission parameters values shall be specified.<br /><br /> If the card is able to process more than one protocol type and if one of<br /> those protocol types is indicated as T=0, then the protocol type T=0 shall<br /> indicated in TD1 as the first offered protocol, and is assumed if no PTS<br /> is performed.<br /><br /> If a card offers more than one protocol and if the interface device<br /> supports only one of these protocols which is not T=0 and does not support<br /> PTS, the interface should reject or reset the card.<br /><br /> 2.3.5.a - PTS protocol<br /> ------------<br /> Only the interface device is permitted to start a PTS procedure:<br /><br /> - The interface device sends a PTS request to the card.<br /> - If the card receives a correct PTS request, it answers by sending a<br /> PTS confirm, if implemented or the initial waiting time will be<br /> exceeded.<br /> - After the succesfull exchange of PTS request and PTS confirm, data<br /> shall be transmitted from the interface device using the selected<br /> protocol type and/or transmission parameters.<br /> - If the card receives an erronous PTS request, it will not send a PTS<br /> confirm.<br /> - If the initial waiting time is exceeded, the interface device should<br /> resetor reject the card.<br /> - If the interface device receives an erroneous PTS confirm, it should<br /> reset or reject the card.<br /><br /> The parameters for the transmission of the PTS request and PTS confirm<br /> shall correspond to those used within the Answer to Reset regarding the<br /> bit rate and the convention detected by TS and possibly modified by TC1.<br /><br /> 2.3.5.b - Structure and content of PTS request and PTS confirm<br /> ----------------------------------------------------<br /> The PTS request and PTS response each consist of one initial character<br /> PTSS, followed by a format character PTS0, three optional parameter<br /> characters PTS1 PTS2 PTS3, and a character check PCK at the last byte.<br /><br /> PTSS identifies the PTS request or PTS confirm and is coded FF.<br /><br /> PTS0 indicates by the bits b5, b6, b7 set to 1 the presence of the<br /> subsequently sent optional characters PTS1, PTS2, PTS3 respectively. It<br /> codes over the least significant bits b4 to b1 the selected protocol type<br /> T as coded in TD bytes. The most significant bit b8 (default b8=0) is<br /> reserved for future use.<br /><br /> PTS1 codes the parameter values FI and D as coded in TA1. The interface<br /> device may send PTS1 in order to indicate the selection FI and/or D values<br /> to the card. If PTS1 is not sent, FI=1 and D=1 are assumed as defaults.<br /> The card either acknowledges both the FI and D values by echoing PTS1 or<br /> does not send PTS1 indicating the use of the default values.<br /><br /> PTS2 indicates the support of N=255, when bit b1 is set to 1. Bit b1 set<br /> to 0 is the default and indicates that the 11 etu period is not used. If<br /> bit b2 is set to 1, the card shall use an extra guardtime of 12 etu for<br /> its transmssion of characters to the interface device. Bit b2 set to 0 is<br /> the default and indicates that no extra guardtime is required. Bit b3 to<br /> b8 are reserved for future use.<br /><br /> If PTS2 is sent by the interface device and is not echoed by the card, the<br /> interface device should reject or reset the card.<br /><br /> The coding and use of PTS3 is not defined.<br /><br /> The value of PCK shall be such that the exclusive-oring of all charcters<br /> from PTSS to PCK included is null.<br /><br /><br /> 2.3.6) Protocol type T=0, asynchronous half duplex character transmission<br /> protocol----------------------------------------------------------<br /> --------<br /> This clause defines the structure and processing of commands initiated by<br /> an interface device for transmission control and for card specific control<br /> in an asynchronous half duplex character transmission protocol.<br /><br /> This protocol uses the parameters indicated by the answer to reset, unless<br /> modified by the protocol type selection.<br /><br /> 2.3.6.a - Specific interface parameters: the work waiting time<br /> ----------------------------------------------------<br /> In an answer to reset, the interface character TC2 codes the integer value<br /> WI over eight bits b8 to b1. When no TC2 appears in the answer to reset,<br /> the default value of WI is 10.<br /><br /> The interval between the start leading edge of any character sent by the<br /> card and the start leading edge of the previous character (sent either by<br /> the card or by the interface device) shall not exceed 960*OWI work etu.<br /> This maximum delay is named the work waiting time.<br /><br /> 2.3.6.b - Structure and processing of commands<br /> ------------------------------------<br /> A command is always initiated by the interface device. It tells the card<br /> what to do in a 5-byte header, and allow a transfer of data bytes under<br /> control of procedure bytes sent by the card.<br /><br /> It is assumed that the card and the interface device know a priori the<br /> direction of data, in order to ditinguish between instructions for<br /> incoming data transfer (where data enter the card during execution) and<br /> instructions for outgoing data transfers (where data leave the card during<br /> execution).<br /><br /><br />without parity error<br />--------------------<br /><br /> Start Start<br /> _____ _____________________________________ ___________<br /> | | | | Byte i | | |P | | | Byte i+1<br /> |__|__|__|__|__|__|__|__|__|__| guartime |__|___________<br /><br /> Even<br />with a parity error parity<br />------------------- bit<br /> Start Start<br /> _____ ______________________________ Error __ ___________<br /> | | | | Byte i | | |P | | signal | | | Byte i+1<br /> |__|__|__|__|__|__|__|__|__|__| |________| |__|___________<br /><br /><br /> Figure 8 : Byte transmission diagram<br /> --------<br /><br /> * Command header sent by the interface device<br /> """""""""""""""""""""""""""""""""""""""""""<br /> The interface device transmits a header over five successive bytes<br /> designated CLA, INS, A1, A2, L.<br /><br /> - CLA is an instruction class. The value FF is reserved for PTS.<br /><br /> - INS is an instruction code in the instruction class. The instruction<br /> code is valid only if the least significant bit is 0, and the most<br /> significant half byte is neither 6 nor 9.<br /><br /> - P1, P2 are a reference (e.g. an address) completing the instruction<br /> code<br /><br /> - P3 codes the number n of data bytes (D1, ... , Dn) which are to be<br /> transmitted during the command. The direction of movement of these<br /> data is a function of the instruction. In an outgoing data transfer<br /> command, P3=0 introduces a 256 byte data transfer from the card. In an<br /> incoming data transfer command, P3=0 introduces no transfer of data.<br /><br /> All remaining encoding possibilities for the header are specified in<br /> subsequent parts of ISO7816.<br /><br /> After transmission of such 5 byte header, the interface device waits for<br /> a procedure byte.<br /><br /> * Procedure bytes sent by the card<br /> """"""""""""""""""""""""""""""""<br /> The value of the procedure bytes shall indicate the action requested by<br /> the interface device. Three types of procedure bytes are specified:<br /><br /> - ACK : (The seven most significant bits in an ACK byte are all equal or<br /> complementary to those in the INS byte, apart from the values 6x and<br /> 9x) The interface device control VPP state and exchanges data<br /> depending on ACK values.<br /><br /> - NULL : (=$60) This byte is sent by the card to restart the working<br /> time, end to anticipate a subsequent procedure byte. It requests no<br /> further action neither on VPP nor on Data.<br /><br /> - SW1 (= $6x or $9x, expect $60); The interface device maintains or sets<br /> VPP at idle and waits for a SW2 byte to complete the command.<br /><br /> Any transition of VPP state (active/idle) must occur within the<br /> guardtime of the procedure byte, or on the work waiting time overflow.<br /><br /> At each procedure byte, the card can proceed with the command by an ACK<br /> or NULL byte, or show its disaproval by becoming unresponsive, or<br /> conclude by an end sequence SW1-SW2.<br /><br /> Byte | Value | Result<br /> -----+-------+------------------------------------------------------------<br /> | INS | VPP is idle. All remaining data bytes are transferred<br /> | | subsequently.<br /> | |<br /> | INS+1 | VPP is active. All remaining data bytes are transferred<br /> | | subsequently.<br /> ACK | ___ |<br /> | INS | VPP is idle. Next data byte is transferred subsequently.<br /> | _____ |<br /> | INS+1 | VPP is active. Newt data byte is transferred subsequently.<br /> -----+-------+------------------------------------------------------------<br /> NULL | $60 | No futher action on VPP. The interface device waits for a<br /> | | new procedure byte<br /> -----+-------+------------------------------------------------------------<br /> SW1 | SW1 | VPP is idle. The interface device waits for a SW2 byte<br /><br /><br /> Acknoledge bytes<br /> ----------------<br /> The ACK bytes are used to control VPP state and data transfer.<br /><br /> - When exclusive-oring the ACK byte with the INS byte gives $00 or<br /> $FF, the interface device maintains or sets VPP as idle.<br /><br /> - When exclusive-oring the ACK byte with the INS byte gives $01 or<br /> $FE, the interface device maintains or sets VPP as active.<br /><br /> - When the seven most significant bits in the ACK byte have the same<br /> value as those in the INS byte, all remaining data bytes (Di, ...,<br /> Dn) if any remain, are transferred subsequently.<br /><br /> - When the seven most significant bits in the ACK byte are<br /> complementary to those in the INS byte, only the next data byte<br /> (Di), if one remains is transferred.<br /><br /> After these actions, the interface device waits for a new procedure.<br /><br /> Null byte (= $60)<br /> -----------------<br /> This byte is sent by the card to reset the workwaiting time and to<br /> anticipate a subsequent procedure byte.<br /><br /> Status bytes (SW1=$6x or $9x, expect $60; SW2 any value)<br /> --------------------------------------------------------<br /> The end sequence SW1-SW2 gives the card status at the end of the command.<br /><br /> The normal ending is indicated by SW1-SW2 = $90-$00.<br /><br /> When the most significant half byte SW1 is $6, the meaning of SW1 is<br /> independant of the application. The following five values are defined:<br /><br /> $6E The card does not support the instruction class.<br /> $6D The instruction code is not programmed or is invalid.<br /> $6B The reference is incorrect.<br /> $67 The length is incorrect.<br /> $6F No precise diagnostic is given.<br /><br /> Other values are reserved for future use by ISO7816.<br /> When SW1 is neither $6E nor $6D, the card support the instruction.<br /> This part of ISO7816 does not interprets neither $9X SW1 bytes, nor SW2<br /> bytes; Their meaning relates to the application itself.<br /><br /> Supplement (were seen sometimes):<br /> ---------------------------------<br /> SW1 SW2 Meaning<br /><br /> 62 81 Returned data may be corrupted.<br /> 62 82 The end of the file has been reached before the end of reading.<br /> 62 84 Selected file is not valid.<br /> 65 01 Memory failure. There have been problems in writing or reading<br /> the EEPROM. Other hardware problems may also bring this error.<br /> 68 00 The request function is not supported by the card.<br /> 6A 00 Bytes P1 and/or P2 are incorrect.<br /> 6A 80 The parameters in the data field are incorrect.<br /> 6A 82 File not found.<br /> 6A 83 Record not found.<br /> 6A 84 There is insufficient memory space in record or file.<br /> 6A 87 The P3 value is not consistent with the P1 and P2 values.<br /> 6A 88 Referenced data not found.<br /> 6C XX Incorrect P3 length.<br />
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