最近也在用Rocket I/O,关于仿真,如果是在FPGA侧做回环,例化时:
//-------------- Transmit Ports - 8b10b Encoder Control Ports --------------
.TILE0_TXCHARISK0_IN (tile0_rxcharisk0_i),
.TILE0_TXCHARISK1_IN (tile0_rxcharisk1_i),
//---------------- Transmit Ports - TX Data Path interface -----------------
.TILE0_TXDATA0_IN (tile0_rxdata0_i),
.TILE0_TXDATA1_IN (tile0_rxdata1_i),
.TILE0_TXOUTCLK0_OUT (tile0_txoutclk0_i),
.TILE0_TXOUTCLK1_OUT (tile0_txoutclk1_i),
.TILE0_TXUSRCLK0_IN (tile0_rxusrclk0_i),
.TILE0_TXUSRCLK1_IN (tile0_rxusrclk0_i),
.TILE0_TXUSRCLK20_IN (tile0_rxusrclk20_i),
.TILE0_TXUSRCLK21_IN (tile0_rxusrclk20_i),
就可以了,仿真没有问题。
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