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这是一个VHDL语言的8bit加法器的code，怎么看不见哪里有加法的说明？<br /><br />library ieee;<br />use ieee.std_logic_1164.all;<br />use ieee.numeric_std.all;<br /><br />ENTITY top IS<br /><br /> port (<br /> DataA: in std_logic_vector(7 downto 0); <br /> DataB: in std_logic_vector(7 downto 0); <br /> Result: out std_logic_vector(7 downto 0));<br /><br />END top;<br /><br />architecture example of top is<br /><br /> component add8<br /> port (DataA: in std_logic_vector(7 downto 0); <br /> DataB: in std_logic_vector(7 downto 0); <br /> Result: out std_logic_vector(7 downto 0));<br /> end component;<br /><br />begin<br /> -- Instantiate Lattice module<br /> add8_1: add8 port map(<br /> DataA => DataA,<br /> DataB => DataB,<br /> Result => Result);<br /><br />end example; |
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