这是一个VHDL语言的8bit加法器的code，怎么看不见哪里有加法的说明？
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY top IS
port (
DataA: in std_logic_vector(7 downto 0);
DataB: in std_logic_vector(7 downto 0);
Result: out std_logic_vector(7 downto 0));
END top;
architecture example of top is
component add8
port (DataA: in std_logic_vector(7 downto 0);
DataB: in std_logic_vector(7 downto 0);
Result: out std_logic_vector(7 downto 0));
end component;
begin
-- Instantiate Lattice module
add8_1: add8 port map(
DataA => DataA,
DataB => DataB,
Result => Result);
end example; |
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