本帖最后由 jakfens 于 2012-2-16 14:19 编辑
哦哦 主要是那个接受的时候他说要在数据下降沿的时候判断开始位 这个文档上面的几句代码不是太了解
自己画了下时序图 楞是没搞出来- First, the incoming "RxD" signal has no relationship with our clock.
- We use two D-flipflops to oversample it, and synchronize it to our clock.
- reg [1:0] RxD_sync;
- always @(posedge clk) if(Baud8Tick) RxD_sync <= {RxD_sync[0], RxD};
- We filter the data, so that short spikes on the RxD line aren't mistaken with start bits.
- reg [1:0] RxD_cnt;
- reg RxD_bit;
- always @(posedge clk)
- if(Baud8Tick)
- begin
- if(RxD_sync[1] && RxD_cnt!=2'b11) RxD_cnt <= RxD_cnt + 1;
- else
- if(~RxD_sync[1] && RxD_cnt!=2'b00) RxD_cnt <= RxD_cnt - 1;
- if(RxD_cnt==2'b00) RxD_bit <= 0;
- else
- if(RxD_cnt==2'b11) RxD_bit <= 1;
- end
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楼主
