|
测试脚本代码：
`timescale 1 ns/ 1 ps
module cy4_vlg_tst();
reg [2:0] A;
reg [2:0] E;
wire [7:0] Y;
cy4 i1 (
.A(A),
.E(E),
.Y(Y)
);
initial
begin
E = 3’b111;
1000;A = 3’b000; 100;A = 3’b001; 100;A = 3’b010; 100;A = 3’b011; 100;A = 3’b100; 100;A = 3’b101; 100;A = 3’b110; 100;A = 3’b111; 100;<span id="MathJax-Element-1-Frame" tabindex="0" data-mathml="stop;" role="presentation" style="box-sizing: border-box; border: 0px; font: inherit; vertical-align: baseline; position: relative;">stop;stop;display(“Running testbench”);
end
endmodule
| 
楼主
