下面是自带的BSP示例中采用的寄存器配置
- /* Enable Internal RC 22.1184MHz clock */
- CLK->PWRCON |= CLK_PWRCON_OSC22M_EN_Msk;
- /* Waiting for Internal RC clock ready */
- while(!(CLK->CLKSTATUS & CLK_CLKSTATUS_OSC22M_STB_Msk));
- /* Switch HCLK clock source to Internal RC and and HCLK source divide 1 */
- CLK->CLKSEL0 &= ~CLK_CLKSEL0_HCLK_S_Msk;
- CLK->CLKSEL0 |= CLK_CLKSEL0_HCLK_S_HIRC;
- CLK->CLKDIV &= ~CLK_CLKDIV_HCLK_N_Msk;
- CLK->CLKDIV |= CLK_CLKDIV_HCLK(1);
- /* Enable external XTAL 12MHz clock */
- CLK->PWRCON |= CLK_PWRCON_XTL12M_EN_Msk;
- /* Waiting for external XTAL clock ready */
- while(!(CLK->CLKSTATUS & CLK_CLKSTATUS_XTL12M_STB_Msk));
- /* Set core clock as PLL_CLOCK from PLL */
- CLK->PLLCON = PLLCON_SETTING;
- while(!(CLK->CLKSTATUS & CLK_CLKSTATUS_PLL_STB_Msk));
- CLK->CLKSEL0 &= (~CLK_CLKSEL0_HCLK_S_Msk);
- CLK->CLKSEL0 |= CLK_CLKSEL0_HCLK_S_PLL;
- /* Update System Core Clock */
- /* User can use SystemCoreClockUpdate() to calculate PllClock, SystemCoreClock and CycylesPerUs automatically. */
- //SystemCoreClockUpdate();
- PllClock = PLL_CLOCK; // PLL
- SystemCoreClock = PLL_CLOCK / 1; // HCLK
- CyclesPerUs = PLL_CLOCK / 1000000; // For SYS_SysTickDelay()
- /* Enable UART module clock */
- CLK->APBCLK |= CLK_APBCLK_UART0_EN_Msk;
- /* Select UART module clock source */
- CLK->CLKSEL1 &= ~CLK_CLKSEL1_UART_S_Msk;
- CLK->CLKSEL1 |= CLK_CLKSEL1_UART_S_HXT;
按照上面的意思,使用库函数替换
- CLK_EnableXtalRC(CLK_PWRCON_OSC22M_EN_Msk);
- CLK_WaitClockReady(CLK_CLKSTATUS_OSC22M_STB_Msk);
- CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_HIRC,CLK_CLKDIV_HCLK(1));
-
- CLK_EnableXtalRC(CLK_PWRCON_XTL12M_EN_Msk);
- CLK_WaitClockReady(CLK_CLKSTATUS_XTL12M_STB_Msk);
-
- CLK_EnablePLL(CLK_PLLCON_PLL_SRC_HXT,FREQ_50MHZ);
- CLK_SetCoreClock(FREQ_50MHZ);
- CLK_EnableModuleClock(UART0_MODULE);
- CLK_SetModuleClock(UART0_MODULE,CLK_CLKSEL1_UART_S_HXT,CLK_CLKDIV_UART(1));
你更喜欢哪一种风格呢?
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