[Actel FPGA] 求解verilog

`include "adder.v"

module adder_tb();

reg[3:0]addend,adder;//加数和被加数

reg a1,a2,a3,a4,b1,b2,b3,b4,c0;//各个位和初始进位

initial

begin

addend=4'b0001;//被加数为1

adder=4'b0010;//加数为2

c0=1'b0;

a1=addend[0];

a2=addend[1];

a3=addend[2];

a4=addend[3];

b1=adder[0];

b2=adder[1];

b3=adder[2];

b4=adder[3];

end

adder m(.a1(a1),.a2(a2),.a3(a3),.a4(a4),.b1(b1),.b2(b2),.b3(b3),.b4(b4),.c0(c0));//调用

endmodule

module adder(a1,a2,a3,a4,b1,b2,b3,b4,c0,sum);

input a1,a2,a3,a4,b1,b2,b3,b4,c0;

output[4:0] sum;

reg[4:0] sum;

wire c1,c2,c3,c4;//中间进位

always@(*)

sum[0]=((~a1)&(~b1)&c0)|((~a1)&b1&(~c0))|(a1&(~b1)&(~c0))|(a1&b1&c0);

always@(*)

sum[1]=((~a2)&(~b2)&c1)|((~a2)&b2&(~c1))|(a2&(~b2)&(~c1))|(a2&b2&c1);

always@(*)

sum[2]=((~a3)&(~b3)&c2)|((~a3)&b3&(~c2))|(a3&(~b3)&(~c2))|(a3&b3&c2);

always@(*)

begin

sum[3]=((~a4)&(~b4)&c3)|((~a4)&b4&(~c3))|(a4&(~b4)&(~c3))|(a4&b4&c3);

sum[4]=c4;

end

assign c1=(a1&b1)|(a1&(~b1)&c0)|((~a1)&b1&c0);

assign c2=(a2&b2)|(a2&(~b2)&c1)|((~a2)&b2&c1);

assign c3=(a3&b3)|(a3&(~b3)&c2)|((~a3)&b3&c2);

assign c4=(a4&b4)|(a4&(~b4)&c3)|((~a4)&b4&c3);

endmodule