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下面这个程序，搞了一个星期了，弄不定啊，用过许多方法。<br />功能主要在always区里，<br />当fir_start来时，说明一个周期的开始。之后，会接着有fir_done的脉冲，每个脉冲来后，wraddress的值加一。<br />可是下明的程序，仿真看，地址就是不加。<br />请高手，帮忙看看！<br /><br />module fir_output_buffer(<br /> clk,<br /> fir_data,<br /> fir_done,<br /> fir_enable,<br /> fir_start,<br /> rdaddress321,<br /> rdclock,<br /> wrclock,<br /> q,<br /> rst);<br /> <br /> input [19:0] fir_data;<br /> input fir_done,fir_start,clk,rst;<br /> output fir_enable;<br /> input [3:0] rdaddress321;<br /> input rdclock;<br /> output [19:0] q;<br /> output wrclock;<br /> <br /> wire [4:0] rdaddress;<br /> reg rdaddress4;<br /> reg fir_enable;<br /> reg wrclock;<br /> reg wren;<br /> wire [19:0] fir_data;<br /> reg [4:0] wraddress;<br /> <br /> assign rdaddress={rdaddress4,rdaddress321};<br /> tx_ram txram1(fir_data,rdaddress,rdclock,wraddress,wrclock,1,q);<br /> <br /> reg fir_start_pre,fir_done_pre; <br /> <br /> always @(posedge clk) <br /> begin<br /> fir_start_pre<=fir_start;<br /> fir_done_pre<=fir_done; <br /> if(rst)<br /> currentstate<=0;<br /> <br /> if(fir_start!=fir_start_pre&&fir_start)<br /> begin<br /> wraddress<=0;<br /> end<br /> <br /> if(fir_done!=fir_done_pre&&fir_done)<br /> begin<br /> wrclock<=1;<br /> wraddress<=wraddress+1;<br /> end<br /> <br /> if(wrclock)<br /> wrclock<=0;<br /> end<br />endmodule<br /><br /> |
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楼主
