#ifdef GD32F10X_CL
/* Configure PLLs ------------------------------------------------------*/
/* PLL configuration: PLLCLK = PREDIV1 * 9 = 108 MHz */
RCC->GCFGR &= (uint32_t)~(RCC_GCFGR_PLLPREDV | RCC_GCFGR_PLLSEL | RCC_GCFGR_PLLMF);
RCC->GCFGR |= (uint32_t)(RCC_GCFGR_PLLPREDV_PREDIV1 | RCC_GCFGR_PLLSEL_PREDIV1 | RCC_GCFGR_PLLMF9);
/* PLL2 configuration: PLL2CLK = (HSE / 5) * 12 = 60 MHz */
/* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 12 MHz */
RCC->GCFGR2 &= (uint32_t)~(RCC_GCFGR2_PREDV2 | RCC_GCFGR2_PLL2MF |
RCC_GCFGR2_PREDV1 | RCC_GCFGR2_PREDV1SEL);
RCC->GCFGR2 |= (uint32_t)( RCC_GCFGR2_PREDV2_DIV5 | RCC_GCFGR2_PLL2MF12 |
RCC_GCFGR2_PREDV1SEL_PLL2 | RCC_GCFGR2_PREDV1_DIV5);
/* Enable PLL2 */
RCC->GCCR |= RCC_GCCR_PLL2EN;
/* Wait till PLL2 is ready */
while((RCC->GCCR & RCC_GCCR_PLL2STB) == 0) //死在这了
{
}
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