用QuartusII编译说 <br />Error (10500): VHDL syntax error at ep111.vhd(49) near text "when"; expecting ";" <br /><br />程序如下:: <br /><br />library IEEE; <br />use IEEE.STD_LOGIC_1164.ALL; <br />use IEEE.STD_LOGIC_ARITH.ALL; <br />use IEEE.STD_LOGIC_UNSIGNED.ALL; <br /><br />entity ep111 is <br />Port ( clk : in STD_LOGIC; <br />reset : in STD_LOGIC; <br />dir : in STD_LOGIC; <br />A : out STD_LOGIC; <br />B : out STD_LOGIC; <br />C : out STD_LOGIC); <br />end ep111; <br /><br />architecture Behavioral of ep111 is <br />Signal abc : STD_LOGIC_VECTOR(2 DOWNTO 0); <br />begin <br /><br />process(clk,reset) <br />begin <br />if rising_edge(clk) then <br />if reset='1' then <br />abc <= "100"; <br />elsif dir='0' then <br />abc <= "110" when abc="100" else <br />--就是这里有问题 <br />"010" when abc="110" else <br />"011" when abc="010" else <br />"001" when abc="011" else <br />"101" when abc="001" else <br />"100" when abc="101" else <br />"000"; <br />elsif dir='1' then <br />abc <= "101" when abc="100" else <br />"001" when abc="101" else <br />"011" when abc="001" else <br />"010" when abc="011" else <br />"110" when abc="010" else <br />"100" when abc="110" else <br />"000"; <br />end if; <br />end if; <br />end process; <br /><br />A <= abc(2); <br />B <= abc(1); <br />C <= abc(0); <br /><br />end Behavioral; |
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