创新型架构高性能/高性价比多通道 DDC IP核技术

主要创新点： 32-Channel DDC 64-Channel DDC可集成到单片300万等效逻辑门的Xilinx或Altera FPGA中，功耗2.5～3W 有需要的可以联系QQ:39650917,email:pornanier@163.com 还可根据客户的不同带宽等特定需求定制通道数（4/8/16/32/64通道） 技术指标（64通道核）： • Two 16-bits ADC inputs, Fs > 220MS/s • 64 independently configurable channels • Independent tuning, gain, sample rate and output filter selection controls • Output sample rates from Fs/128 to Fs/8192 or more • Maximum alias-free output bandwidth of Fs/320 (= 625kHz for Fs = 200MS/s) • 8 programmable output shaping filters • Example filter performance: 0.1dB peak to peak ripple, alias-free bandwidth 80% of output sample rate and 90dB image rejection • Centre frequency tuning accuracy to within 0.012Hz（Fs/2^34） • Resampling provides any output rate to within 0.012Hz（Fs/2^34） • >90dB spurious free end to end performance • Resampled output maintains >90dB spurious free performance • 0 to 90dB gain boost MGC & AGC 应用xilinx的V6，输入采样率可达350MSPS，32通道版本可以满足TD－SCDMA系统的带宽要求（最大抗混叠带宽为Fs/160）

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