本帖最后由 34af9uc 于 2024-2-19 22:51 编辑
程序我是理解不了13,14有警告忽略,技术告诉忽略!!!别忘了绑定管脚,不然没有输出~~~~~~~~
- module LED
- (
- // input clk,
- output reg led
- );
- wire sys_clk;
- wire clko;
- // OSC_DIV u_oscdiv( .rstn(1), .stdby(0), .div(7'b000_0100), .clko(clko) );
- EF2_PHY_OSCDIV inst(
- .rstn(1),
- .stdby(0),
- .div(7'b000_0100),
- .clko(clko));
- EF2_LOGIC_BUFG BUFG_inst(
- .o(sys_clk),
- .i(clko)
- );
- reg[24:0] cnt;
- always@(posedge sys_clk) //上升沿
- begin
- if(cnt==5_000_000) //0.5秒
- begin
- cnt <=0;
- led <=~led;
- end
- else
- cnt <=cnt +1;
- end
- endmodule
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