library ieee;<br />use ieee.std_logic_1164.all;<br />use ieee.std_logic_unsigned.all;<br />entity haohao is<br /> port(clkk:in std_logic;<br /> ret:in std_logic;<br /> clk1hz:out std_logic);<br />end haohao;<br />architecture behav of haohao is<br />signal div2clk : integer range 7 downto 0;<br /> signal kk1: std_logic;<br />begin<br />process(clkk,ret)<br />begin<br /> if ret='1' then kk1<='0';<br />elsif div2clk=5 then kk1<=not kk1; div2clk<=0;<br />elsif clkk'event and clkk='1' then div2clk<=div2clk+1;<br />end if;<br />end process;<br />clk1hz<=kk1;<br />end behav; |
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