楼主还是仔细研读datasheet里的时钟部分吧,很多东西真的很难
您可以参考“Clock Generator Block Diagram”,外部输入时钟经PLL倍频,分频得到 FCLK:HCLK:PCLK.<br /><br />FCLK is used by ARM920T.<br />HCLK is used for AHB bus, which is used by the ARM920T, the memory controller, the interrupt controller, the<br />LCD controller, the DMA and USB host block.<br />PCLK is used for APB bus, which is used by the peripherals such as WDT, IIS, I2C, PWM timer, MMC interface,<br />ADC, UART, GPIO, RTC and SPI.<br /><br />TCLK是由外围时钟(PCLK)分频得到的,作为定时器的记数时钟,说白了就是当TCLK震荡一次,定时器的计数值就递增1
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