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mcu DMA spi rc gd32F103 ISO
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2021-04-07
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void init_spi_slave(void)
{
spi_parameter_struct spi_init_struct;
//打开spi口GPIO的时钟
rcu_periph_clock_enable(RCU_GPIOA);
//打开spi口外设的时钟
rcu_periph_clock_enable(clk_spi_slave);
//Configure SPI_SLAVE pins: NSS, SCK and MOSI
gpio_init(GPIOA, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_10MHZ, GPIO_Pin_5);
gpio_init(GPIOA, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_10MHZ, GPIO_Pin_7);
//cs
gpio_init(GPIOA, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_10MHZ, GPIO_Pin_4);
//MISO
gpio_init(GPIOA, GPIO_MODE_AF_PP, GPIO_OSPEED_10MHZ, GPIO_Pin_6);
spi_i2s_deinit(spi_slave);
spi_struct_para_init(&spi_init_struct);
spi_init_struct.trans_mode = SPI_TRANSMODE_FULLDUPLEX;
spi_init_struct.device_mode = SPI_SLAVE;
spi_init_struct.frame_size = SPI_FRAMESIZE_8BIT;
spi_init_struct.clock_polarity_phase = SPI_CK_PL_LOW_PH_2EDGE;
spi_init_struct.nss = SPI_NSS_SOFT;
spi_init_struct.prescale = SPI_PSC_8;
spi_init_struct.endian = SPI_ENDIAN_MSB;
spi_init(spi_slave, &spi_init_struct);
spi_crc_off(spi_slave);
spi_nss_internal_low(spi_slave);
spi_enable(spi_slave);
}
void spi_slave_rev_start(void)
{
memset(link_rx, 0, 48);
dma_memory_address_config(DMA0, DMA_CH1, (uint32_t)link_rx);
dma_transfer_number_config(DMA0, DMA_CH1, link_rxbuf_len);
dma_channel_enable(DMA0, DMA_CH1);
}
void spi_slave_rev_stop(void)
{
dma_transfer_number_config(DMA0, DMA_CH1, 0);
dma_channel_disable(DMA0, DMA_CH1);
}
void spi_slave_send_start(uint16_t count)
{
dma_memory_address_config(DMA0, DMA_CH2, (uint32_t)link_tx);
dma_transfer_number_config(DMA0, DMA_CH2, count);
dma_channel_enable(DMA0, DMA_CH2);
}
void spi_slave_send_stop(void)
{
dma_transfer_number_config(DMA0, DMA_CH2, 0);
dma_channel_disable(DMA0, DMA_CH2);
}
void init_spi_slave_dma(void)
{
dma_parameter_struct dma_init_struct;
rcu_periph_clock_enable(RCU_DMA0);
dma_deinit(DMA0, DMA_CH1);
dma_struct_para_init(&dma_init_struct);
dma_init_struct.direction = DMA_PERIPHERAL_TO_MEMORY;
dma_init_struct.memory_addr = (uint32_t)link_rx;
dma_init_struct.memory_inc = DMA_MEMORY_INCREASE_ENABLE;
dma_init_struct.memory_width = DMA_MEMORY_WIDTH_8BIT;
dma_init_struct.number = link_rxbuf_len;
dma_init_struct.periph_addr = (uint32_t)&SPI_DATA(spi_slave);
dma_init_struct.periph_inc = DMA_PERIPH_INCREASE_DISABLE;
dma_init_struct.periph_width = DMA_PERIPHERAL_WIDTH_8BIT;
dma_init_struct.priority = DMA_PRIORITY_ULTRA_HIGH;
dma_init(DMA0, DMA_CH1, &dma_init_struct);
dma_circulation_disable(DMA0, DMA_CH1);
dma_memory_to_memory_disable(DMA0, DMA_CH1);
nvic_irq_enable(DMA0_Channel1_IRQn, 6, 0);
dma_interrupt_enable(DMA0, DMA_CH1, DMA_INT_FTF);
dma_interrupt_enable(DMA0, DMA_CH1, DMA_INT_ERR);
dma_deinit(DMA0, DMA_CH2);
dma_struct_para_init(&dma_init_struct);
dma_init_struct.direction = DMA_MEMORY_TO_PERIPHERAL;
dma_init_struct.memory_addr = (uint32_t)link_tx;
dma_init_struct.memory_inc = DMA_MEMORY_INCREASE_ENABLE;
dma_init_struct.memory_width = DMA_MEMORY_WIDTH_8BIT;
dma_init_struct.number = link_txbuf_len;
dma_init_struct.periph_addr = (uint32_t)&SPI_DATA(spi_slave);
dma_init_struct.periph_inc = DMA_PERIPH_INCREASE_DISABLE;
dma_init_struct.periph_width = DMA_PERIPHERAL_WIDTH_8BIT;
dma_init_struct.priority = DMA_PRIORITY_ULTRA_HIGH;
dma_init(DMA0, DMA_CH2, &dma_init_struct);
dma_circulation_disable(DMA0, DMA_CH2);
dma_memory_to_memory_disable(DMA0, DMA_CH2);
nvic_irq_enable(DMA0_Channel2_IRQn, 6, 0);
dma_interrupt_enable(DMA0, DMA_CH2, DMA_INT_FTF);
dma_interrupt_enable(DMA0, DMA_CH2, DMA_INT_ERR);
spi_dma_enable(spi_slave, SPI_DMA_TRANSMIT);
spi_dma_enable(spi_slave, SPI_DMA_RECEIVE);
slave_dma_send_stop();
}
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2021-04-07
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2021-04-07
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