通过把中断向量表放到ram低端, 可以解决问题
91x_vect.s 中的改动:
PROGRAM ?RESET COMMON INTVEC:CODE(2) CODE32
VectorAddress EQU 0xFFFFF030 // VIC Vector address register address. VectorAddressDaisy EQU 0xFC000030 // Daisy VIC Vector address register I_Bit EQU 0x80 // when I bit is set, IRQ is disabled F_Bit EQU 0x40 // when F bit is set, FIQ is disabled
//******************************************************************************* // Import the __program_start address from 91x_init.s //******************************************************************************* IMPORT __program_start //******************************************************************************* // Import exception handlers //******************************************************************************* IMPORT Undefined_Handler IMPORT SWI_Handler IMPORT Prefetch_Handler IMPORT Abort_Handler IMPORT FIQ_Handler
PUBLIC CopyStart PUBLIC CopyEnd //******************************************************************************* // Exception vectors at Boot Flash 0x00000000 //******************************************************************************* LDR PC, Reset_Addr // @0x00000000 LDR PC, Undefined_Addr // @0x00000004 LDR PC, SWI_Addr // @0x00000008 LDR PC, Prefetch_Addr // @0x0000000C LDR PC, Abort_Addr // @0x00000010 LDR PC, Reserve_Addr // @0x00000014 LDR PC, IRQ_Addr // @0x00000018 LDR PC, FIQ_Addr // @0x0000001C Reset_Addr DCD __program_start // @0x00000020 Undefined_Addr DCD 0x04000004 // @0x00000024 SWI_Addr DCD 0x04000008 // @0x00000028 Prefetch_Addr DCD 0x0400000C // @0x0000002C Abort_Addr DCD 0x04000010 // @0x00000030 Reserve_Addr DCD 0x04000014 // @0x00000034 IRQ_Addr DCD 0x04000018 // @0x00000038 FIQ_Addr DCD 0x0400001C // @0x0000003C
//******************************************************************************* // Exception vectors at RAM 0x04000000 : Copy from 0x00000040 : 64 Bytes //******************************************************************************* CopyStart LDR PC, Reset_Addr_RAM // @0x00000040 To 0x04000000 LDR PC, Undefined_Addr_RAM // @0x00000044 To 0x04000004 LDR PC, SWI_Addr_RAM // @0x00000048 To 0x04000008 LDR PC, Prefetch_Addr_RAM // @0x0000004C To 0x0400000C LDR PC, Abort_Addr_RAM // @0x00000050 To 0x04000010 LDR PC, Reserve_Addr_RAM // @0x00000054 To 0x04000014 LDR PC, IRQ_Addr_RAM // @0x00000058 To 0x04000018 LDR PC, FIQ_Addr_RAM // @0x0000005C To 0x0400001C Reset_Addr_RAM DCD __program_start // @0x00000060 To 0x50017FE0 Undefined_Addr_RAM DCD UndefinedHandler // @0x00000064 To 0x50017FE4 SWI_Addr_RAM DCD SWIHandler // @0x00000068 To 0x50017FE8 Prefetch_Addr_RAM DCD PrefetchAbortHandler // @0x0000006C To 0x50017FEC Abort_Addr_RAM DCD DataAbortHandler // @0x00000070 To 0x50017FF0 Reserve_Addr_RAM DCD __program_start // @0x00000074 To 0x50017FF4 IRQ_Addr_RAM DCD IRQHandler // @0x00000078 To 0x50017FF8 FIQ_Addr_RAM DCD FIQHandler // @0x0000007C To 0x50017FFC CopyEnd
//******************************************************************************* // --- Copy Interrupt Vector Table to RAM : 64 bytes 0x04000000..0x0400003F //******************************************************************************* // LDR R0, =CopyStart // LDR R1, =0x04000000 // LDMIA R0!, {R4-R11} // STMIA R1!, {R4-R11} // LDMIA R0!, {R4-R11} // STMIA R1!, {R4-R11}
//******************************************************************************* //* Function Name : FIQHandler //* Description : This function is called when FIQ exception is entered. //* Input : none //* Output : none //******************************************************************************* FIQHandler SUB lr,lr,#4 // Update the link register. STMFD sp!,{r0-r7,lr} // Save The workspace plus the current return // address lr_fiq into the FIQ stack. ldr r0,=FIQ_Handler ldr lr,=FIQ_Handler_end bx r0 //Branch to FIQ_Handler. FIQ_Handler_end:
LDMFD sp!,{r0-r7,pc}^// Return to the instruction following... // ...the exception interrupt.
91x_init.s 改动:
EXTERN CopyStart CODE32
//******************************************************************************* // --- Remap Flash Bank 0 at address 0x0 and Bank 1 at address 0x80000, // when the bank 0 is the boot bank, then enable the Bank 1. //*******************************************************************************
LDR R6, =0x54000000 // ;LDR R7, =0x0 // BOOT BANK Size = 32KB : (2^0) * 32 = 32KB LDR R7, =0x4 // BOOT BANK Size = 512KB : (2^4) * 32 = 512KB STR R7, [R6]
LDR R6, =0x54000004 // ;LDR R7, =0x6 // NON BOOT BANK Size = 512KB : (2^6) * 8 = 512KB ;LDR R7, =0x2 // NON BOOT BANK Size = 32KB : (2^2) * 8 = 322KB LDR R7, =0x3 // NON BOOT BANK Size = 32KB : (2^2) * 8 = 322KB STR R7, [R6]
LDR R6, =0x5400000C // BOOT BANK Address = 0x0 LDR R7, =0x0 STR R7, [R6] // 512KB Align LDR R6, =0x54000010 // NON BOOT BANK Address = 0x80000 LDR R7, =0x20000 // need to put 0x20000 because FMI bus on A[25:2] of CPU bus STR R7, [R6] // --- Enable CS on both banks LDR R6, =0x54000018 LDR R7, =0x18 STR R7, [R6]
// --- Enable 96K RAM LDR R0, = SCRO_AHB_UNB LDR R1, = 0x0191 // PFQBC enabled / DTCM & AHB wait-states disabled STR R1, [R0]
//******************************************************************************* // --- Copy Interrupt Vector Table to RAM : 64 bytes 0x04000000..0x0400003F //******************************************************************************* LDR R0, =CopyStart LDR R1, =0x04000000 LDMIA R0!, {R4-R11} STMIA R1!, {R4-R11} LDMIA R0!, {R4-R11} STMIA R1!, {R4-R11}
// --- Initialize Stack pointer registers
// ---Enter each mode in turn and set up the stack pointer MSR CPSR_c, #Mode_FIQ|I_Bit|F_Bit // No interrupts LDR SP, =SFE(FIQ_STACK) & 0xFFFFFFF8
为了在flash中调试代码, linker confing 修改:
// Code memory in flash -DROMSTART=0x00000000 -DROMEND=0x0007FFFF
// Data memory -DRAMSTART=0x4000040 //保留开始的64字节 -DRAMEND=0x4017FFF
为了在RAM调试 :
// Code and data in RAM -DRAMSTART=0x04000040 //保留开始的64字节 -DRAMEND=0x04017FFF
// Code memory in RAM -DROMSTART=RAMSTART -DROMEND=RAMEND
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