我这段程序运行后，lcd1602只能显示第一行，显示的东西还有错误，所以想求助各位大神，因为刚接触FPGA，我不知道是哪里出错了，请各位大神给予建议和指导啊，谢谢了
module LCD1602(clk, rs, rw, en,dat,LCD_N,LCD_P);
input clk;
output [7:0] dat;
output rs,rw,en,LCD_N,LCD_P;
reg e;
reg [7:0] dat;
reg rs;
reg [15:0] counter;
reg [7:0] current,next;
reg clkr;
reg [31:0] cnt=0;
parameter set0=8'h00;
parameter set1=8'h01;
parameter set2=8'h02;
parameter set3=8'h03;
parameter set4=8'h04;
parameter dat0=8'h05;
parameter dat1=8'h06;
parameter dat2=8'h07;
parameter dat3=8'h08;
parameter dat4=8'h09;
parameter dat5=8'h0A;
parameter dat6=8'h0B;
parameter dat7=8'h0C;
parameter dat8=8'h0D;
parameter dat9=8'h0E;
parameter dat10=8'h0F;
parameter dat11=8'h10;
parameter dat12=8'h11;
parameter dat13=8'h12;
parameter dat14=8'h13;
parameter dat15=8'h14;
parameter dat16=8'h15;
parameter dat17=8'h16;
parameter dat18=8'h17;
parameter dat19=8'h18;
parameter dat20=8'h19;
parameter dat21=8'h1A;
parameter dat22=8'h1B;
parameter dat23=8'h1C;
parameter dat24=8'h1D;
parameter dat25=8'h1E;
parameter dat26=8'h1F;
parameter dat27=8'h20;
parameter nul=8'hFF;
assign LCD_N=0;
assign LCD_P=1;
always @(posedge clk)
begin
counter<=counter+1;
if(counter==16'h000f)
clkr<=~clkr;
end
always @(posedge clkr)
begin
current<=next;
case(current)
set0: begin rs<=0; dat<=8'h31; next<=set1; end
set1: begin rs<=0; dat<=8'h0C; next<=set2; end
set2: begin rs<=0; dat<=8'h6; next<=set3; end
set3: begin rs<=0; dat<=8'h1; next<=dat0; end
dat0: begin rs<=1; dat<="W"; next<=dat1; end
dat1: begin rs<=1; dat<="O"; next<=dat2; end
dat2: begin rs<=1; dat<="S"; next<=dat3; end
dat3: begin rs<=1; dat<="H"; next<=dat4; end
dat4: begin rs<=1; dat<="I"; next<=dat5; end
dat5: begin rs<=1; dat<="H"; next<=dat6; end
dat6: begin rs<=1; dat<="A"; next<=dat7; end
dat7: begin rs<=1; dat<="O"; next<=dat8; end
dat8: begin rs<=1; dat<="R"; next<=dat9; end
dat9: begin rs<=1; dat<="E"; next<=dat10; end
dat10: begin rs<=1; dat<="N"; next<=dat11; end
dat11: begin rs<=1; dat<="!"; next<=dat12; end
dat12: begin rs<=1; dat<="!"; next<=dat13; end
dat13: begin rs<=1; dat<="!"; next<=set4; end
set4: begin rs<=0;dat<=8'hc0;next<=dat14; end//设置第2行地址
dat14: begin rs<=1; dat<="N"; next<=dat15; end
dat15: begin rs<=1; dat<="I"; next<=dat16; end
dat16: begin rs<=1; dat<="S"; next<=dat17; end
dat17: begin rs<=1; dat<="H"; next<=dat18; end
dat18: begin rs<=1; dat<="I"; next<=dat19; end
dat18: begin rs<=1; dat<=":"; next<=dat20; end
dat20: begin rs<=1; dat<="H"; next<=dat21; end
dat21: begin rs<=1; dat<="U"; next<=dat22; end
dat22: begin rs<=1; dat<="A"; next<=dat23; end
dat23: begin rs<=1; dat<="I"; next<=dat24; end
dat24: begin rs<=1; dat<="R"; next<=dat25; end
dat25: begin rs<=1; dat<="E"; next<=dat26; end
dat26: begin rs<=1; dat<="N"; next<=dat27; end
dat27: begin rs<=1; dat<="!"; next<=nul; end
nul: begin rs<=0; dat<=8'h00;
if(cnt!=2'h2)
begin
e<=0;next<=set0;cnt<=cnt+1;
end
else
begin next<=nul; e<=1;
end
end
default: next<=set0;
endcase
end
assign en=clkr|e;
assign rw=0;
endmodule |
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