STM32ZE开辟数组到外部sram 的例子如下，仅供参考：
#define SRAM_MAX_COUNT 0x80000
typedef struct
{
vu16 HalfWord[SRAM_MAX_COUNT];
} BOARD_SRAM_TypeDef;
// Note: SRAM /CS is CE2_1 - Bank 2 of 0~3
#define BOARD_SRAM_BASE ((u32)(0x60000000 | 0x08000000))
#define BOARD_SRAM ((BOARD_SRAM_TypeDef *) BOARD_SRAM_BASE)
//...
void SRAM_Test(void)
{
// 变量定义：此处省略
// SRAM IO configuration --------------------------------------//
// Enable FSMC, GPIOD~G & AFEN(Alternate Function) clock //
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, ENABLE);
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOE |
RCC_APB2Periph_GPIOF | RCC_APB2Periph_GPIOG |
RCC_APB2Periph_AFIO, ENABLE);
// Set PD0,1, 4,5, 8~15 as PP AF - D2,3, OE,WE, D13~15, A16~18, D0~1
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_4 | GPIO_Pin_5 |
GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11 |
GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_Init(GPIOD, &GPIO_InitStructure);
// Set PE0,1, 7~15 as PP AF - BLN0,1, D4~12
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_7 | GPIO_Pin_8 |
GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_12 |
GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15;
// GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
// GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_Init(GPIOE, &GPIO_InitStructure);
// Set PF0~5, 12~15 as PP AF - A0~5, A6~9
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 |
GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_12 | GPIO_Pin_13 |
GPIO_Pin_14 | GPIO_Pin_15;
GPIO_Init(GPIOF, &GPIO_InitStructure);
// Set PG0~5, 10 as PP AF - A10~15, CE2_1
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 |
GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_10;
GPIO_Init(GPIOG, &GPIO_InitStructure);
// SRAM configuration -----------------------------------------//
// SRAM configured as follow:
// - Data/Address MUX = Disable
// - Memory Type = SRAM
// - Data Width = 16bit
// - Write Operation = Enable
// - Extended Mode = Disable
// - Asynchronous Wait = Disable
FSMC_Bank1->BTCR[4] = FSMC_DataAddressMux_Disable | FSMC_MemoryType_SRAM |
FSMC_MemoryDataWidth_16b | FSMC_WriteOperation_Enable |
FSMC_ExtendedMode_Disable | FSMC_AsyncWait_Disable;
// and as follow - for both read & write operations:
// - Address Setup Time = 0x01
// - Address Hold Time = 0x00
// - Data Setup Time = 0x01
// - Bus Turn around Duration = 0x00
FSMC_Bank1->BTCR[5] = 0x00000101; // timing OK for 36M,48M&72M Hz Fcpu
// - BANK 2 (of NOR/SRAM Bank 0~3) is enabled
FSMC_Bank1->BTCR[4] |= 0x0001;
// SRAM test - test a block of SRAM area from SRAM address 0x00000
for(Added_Addr=0; Added_Addr<0x80000; )
{
for(i=0; i<0x80; i++)
{
// write data to SRAM
for(j=0; j<SRAM_BUF_SIZE; j++)
BOARD_SRAM->HalfWord[i+j + Added_Addr] = Sram_WriteBuf[j];
// read data from SRAM
for(j=0; j<SRAM_BUF_SIZE; j++)
Sram_ReadBuf[j] = BOARD_SRAM->HalfWord[i+j + Added_Addr];
// compare read-data with written-data
for(j=0; j<SRAM_BUF_SIZE; j++)
if(Sram_ReadBuf[j] != Sram_WriteBuf[j])
return SRAM_TEST_FAIL_64;
// clear buffer - specific value
for(j=0; j<SRAM_BUF_SIZE; j++)
Sram_ReadBuf[j] = 0x8888;
}
if(Added_Addr==0)
Added_Addr = 0x100;
else
Added_Addr <<= 1;
}
}
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