当初是想试验一下st9的省电模式，没想到会出这种问题。 JTAG的时钟频率应小于CPU时钟频率的十分之一，这没错，但是， To ensure this, the signal JRTCK is output from the STR91xF and is input to the external JTAG test equipment to hold off transitions of JTCK until the CPU core is ready, meaning that the JTAG equipment cannot send the next rising edge of JTCK until the equipment receives a rising edge of JRTCK from the STR91xF. 于是尝试将str9的JRTCK与flash link的相应信号连接。可是仍不行。 难道就没其他办法了吗？
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