一段VHDL程序，仿真正确，下载后不正确

只看该作者 · 2015-9-25 16:43

写了一段程序，仿真完全正确，但是下载到芯片上面，脉冲就是出不来。
--*************************************************************************
-- @file Stepper_Motor.vhd
-- @author
-- @version       v1.21
-- @date 09/24/2015
---************************************************************************

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY stepper_motor IS
--GENERIC(pulse_width:INTEGER:=25000; --脉冲宽度20uS
--    pulse_frequency:INTEGER:=25000); --脉冲频率1ms

PORT( clk:IN STD_LOGIC;
start:IN STD_LOGIC;
en,dir,reset,step_pulse:OUT STD_LOGIC);
END stepper_motor;

ARCHITECTURE control OF stepper_motor IS

SIGNAL state0:INTEGER RANGE 0 TO 7:=0;

BEGIN

p1:PROCESS(clk)

--VARIABLE pulse_width:INTEGER RANGE 0 TO 12500:=0;
VARIABLE uniform_speed:INTEGER RANGE 0 TO 35000:=0; --35000/0.7ms
--VARIABLE pulse_width_cnt:INTEGER RANGE 0 TO 12504:=0;
VARIABLE uniform_speed_cnt:INTEGER RANGE 0 TO 35004:=0;
VARIABLE accelerated_speed_initial:INTEGER RANGE 0 TO 5000000:=0; --5000000/100ms
VARIABLE accelerated_speed_initial_cnt:INTEGER RANGE 0 TO 5000004:=0;
VARIABLE accelerated_speed:INTEGER RANGE 0 TO 49650:=0;

BEGIN
IF clk'EVENT AND clk='1' THEN
CASE state0 IS
WHEN 0 => IF start='0' THEN
state0<=1;
ELSE
state0<=0;
END IF;
WHEN 1 => en<='1';
step_pulse<='0';
dir<='0';
reset<='1';
state0<=2;
--pulse_width:=12500;
uniform_speed:=35000;
--pulse_width_cnt:=0;
uniform_speed_cnt:=0;
accelerated_speed_initial:=5000000;
accelerated_speed_initial_cnt:=0;
accelerated_speed:=49650;
WHEN 2 => IF accelerated_speed_initial_cnt<=accelerated_speed_initial/4 THEN
step_pulse<='1';
accelerated_speed_initial_cnt:=accelerated_speed_initial_cnt+1;
ELSE
   step_pulse<='0';
accelerated_speed_initial_cnt:=0;
state0<=3;
END IF;
WHEN 3 => IF accelerated_speed_initial_cnt<=accelerated_speed_initial*3/4 THEN
accelerated_speed_initial_cnt:=accelerated_speed_initial_cnt+1;
ELSE
accelerated_speed_initial_cnt:=0;
state0<=4;
END IF;
WHEN 4 => IF uniform_speed<accelerated_speed_initial THEN
accelerated_speed_initial:=accelerated_speed_initial-accelerated_speed;
state0<=2;
ELSE
state0<=5;
END IF;
WHEN 5 => IF uniform_speed_cnt<=uniform_speed/2 THEN
step_pulse<='1';
uniform_speed_cnt:=uniform_speed_cnt+1;
ELSE
step_pulse<='0';
uniform_speed_cnt:=0;
state0<=6;
END IF;
WHEN 6 => IF uniform_speed_cnt<=uniform_speed/2 THEN
uniform_speed_cnt:=uniform_speed_cnt+1;
ELSE
uniform_speed_cnt:=0;
state0<=5;
END IF;

WHEN OTHERS => state0<=0;
END CASE;
END IF;

END PROCESS;

END control;