自己先顶一下，在官网下载的Errata sheet对DAC的说明：
1.2.1 Default DAC output level when output buffer is enabled
Description
When the DAC is enabled in buffered mode configuration, the output is set to a voltage
which corresponds to the code 0xFFF, whatever the data output register value. The output
recovers the correct voltage as soon as a new data is written into the data holding register.
Workaround
None.
The following software sequence must be executed at the highest speed to limit the duration
of this transient behavior:
DAC->CR1=01; //Enable DAC
DAC->DHR8 = 0x0; //Update the data holding register with 0 (as
an example), or with any other data.
Note: The DAC in unbuffered mode is not affected by this limitation.
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难道都让每个使用的人自己去发现？
