写8000个数据到片外SRAM，XINTF6，0x10FC00开始
写8000个数据到片内SRAM，0x00E000开始
发现速度一样，都再1500微秒左右。
SRAM最大支持8ns，配置如下
void init_zone6()
{
EALLOW;
// Make sure the XINTF clock is enabled
SysCtrlRegs.PCLKCR3.bit.XINTFENCLK = 1;
EDIS;
// Configure the GPIO for XINTF with a 16-bit data bus
// This function is in DSP2833x_Xintf.c
InitXintf16Gpio();
// All Zones---------------------------------
// Timing for all zones based on XTIMCLK = SYSCLKOUT
EALLOW;
XintfRegs.XINTCNF2.bit.XTIMCLK = 0;//XTIMCLK = SYSCLKOUT
// Buffer up to 3 writes
XintfRegs.XINTCNF2.bit.WRBUFF = 3; //3级写缓冲
// XCLKOUT is enabled
XintfRegs.XINTCNF2.bit.CLKOFF = 0;//XCLKOUT使能
// XCLKOUT = XTIMCLK
XintfRegs.XINTCNF2.bit.CLKMODE = 0;//XCLKOUT = XTIMCLK
// Zone 6------------------------------------
// When using ready, ACTIVE must be 1 or greater
// Lead must always be 1 or greater
// Zone write timing =150/(1+2+1+1)=30Mhz
XintfRegs.XTIMING6.bit.XWRLEAD = 1;//建立周期数为1
XintfRegs.XTIMING6.bit.XWRACTIVE = 2;//激活周期数为2
XintfRegs.XTIMING6.bit.XWRTRAIL = 1;//跟踪周期数为1
// Zone read timing =150/(1+3+0+1)=30Mhz
XintfRegs.XTIMING6.bit.XRDLEAD = 1;
XintfRegs.XTIMING6.bit.XRDACTIVE = 3;
XintfRegs.XTIMING6.bit.XRDTRAIL = 0;
// don't double all Zone read/write lead/active/trail timing
XintfRegs.XTIMING6.bit.X2TIMING = 0;
// Zone will not sample XREADY signal
XintfRegs.XTIMING6.bit.USEREADY = 0;
XintfRegs.XTIMING6.bit.READYMODE = 0;
// 1,1 = x16 data bus
// 0,1 = x32 data bus
// other values are reserved
XintfRegs.XTIMING6.bit.XSIZE = 3;
EDIS;
//Force a pipeline flush to ensure that the write to
//the last register configured occurs before returning.
asm(" RPT #7 || NOP");
}
程序如下
for(b=0;b<500;b++)
{
for(a=0;a<16;a++)
{
*DMADest++ = *DMASource++;
}
DMASource = &DMABuf2[0];
}
数据都搬过去了
不是说片外比较慢么…… |
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