library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity smgshuzhi is
port ( clk:in std_logic;
cout:in std_logic;
data1,data2,data3,data4 :out integer range 0 to 99);
end smgshuzhi;
architecture arch of smgshuzhi is
begin
daoshi:process(cout)
VARIABLE jishuu :INTEGER RANGE 0 TO 125;
VARIABLE datazs1,datazs2,datazs3,datazs4 :INTEGER RANGE 0 TO 99;
begin
if jishuu=0 then
datazs1:=47;datazs2:=62;datazs3:=30;datazs4:=62;
elsif jishuu=30 then datazs3:=3;
elsif jishuu=33 then datazs3:=92;
elsif jishuu=47 then datazs1:=3;
elsif jishuu=50 then datazs1:=75;
elsif jishuu=62 then datazs2:=43;datazs4:=31;
elsif jishuu=93 then datazs4:=3;
elsif jishuu=96 then datazs4:=91;
elsif jishuu=105 then datazs2:=3;
elsif jishuu=108 then datazs2:=79;
else null;
end if;
if cout'event and cout='1'
then datazs1:=datazs1-1;datazs2:=datazs2-1;datazs3:=datazs3-1;datazs4:=datazs4-1;
jishuu:=jishuu+1;end if;
data1<=datazs1;data2<=datazs2;data3<=datazs3;data4<=datazs4;
end process daoshi;
end arch;
错误提示是
Error (10818): Can't infer register for "daoshi:datazs2[3]" at smgshuzhi.vhd(30) because it does not hold its value outside the clock edge
…………
把信号data1-data4设置成内部信号,不是out 居然就能编译通过了。。。但是如果再在另一个进程中赋值内部信号的值给out 又会报错。。。 |