流水灯程序如下
library IEEE;
use IEEE.std_logic_1164.all;--该库定义了std_logic(8值)和std_ulogic（9值）多值逻辑结构
--------------------------------------------------------------------------------------------------
entity LEDWATER is
port (
Clk : in STD_LOGIC; --创建时钟端口，连接开发板PIN23
Rst : in STD_LOGIC; --创建复位端口，连接开发板PIN116
Output : out STD_LOGIC_VECTOR(7 downto 0) --创建输出端口，连接开发板PIN142-PIN133
);
end LEDWATER;
--------------------------------------------------------------------------------------------------
architecture BEHAVIOR_LEDWATER of LEDWATER is
signal Clk1 : STD_LOGIC; --建立中间时钟信号
begin
P1: process(Clk) --进程1，对时钟信号进行N分频
variable count : INTEGER range 0 to 25 := 0;--变量初始值不可综合，在仿真中使用
variable count1: STD_LOGIC := '1';
begin
if(Rst = '0') then
count := 0;
elsif(Clk'event and Clk = '1') then
count := count + 1;
if(count = 25) then
count := 0;
count1:= not count1;
end if;
Clk1 <= count1;
end if;
end process;
P2: process(Clk1) --进程2，对分频信号进行计数，进而控制LED亮灭
variable count2 : INTEGER range 0 to 8 := 0;--变量初始值不可综合，在仿真中使用
begin
if(Clk1'event and Clk1 = '1') then
count2 := count2 + 1;
if(count2 = 8) then
count2 := 0;
end if;
end if;
case count2 is
when 0 => Output <= "11111110";
when 1 => Output <= "11111101";
when 2 => Output <= "11111011";
when 3 => Output <= "11110111";
when 4 => Output <= "11101111";
when 5 => Output <= "11011111";
when 6 => Output <= "10111111";
when 7 => Output <= "01111111";
when others => Output <= (others => 'Z');
end case;
end process;
end BEHAVIOR_LEDWATER;
自己写的testbench如下：
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:51:38 11/12/2015
-- Design Name:
-- Module Name: D:/FPGA_Projects/LEDonNET/test.vhd
-- Project Name: LEDonNET
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: LEDWATER
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY test IS
END test;
ARCHITECTURE behavior OF test IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT LEDWATER
PORT(
Clk : IN std_logic;
Rst : IN std_logic;
Output : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal Clk : std_logic := '0';
signal Rst : std_logic := '0';
--Outputs
signal Output : std_logic_vector(7 downto 0);
-- Clock period definitions
constant Clk_period : time := 1 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: LEDWATER PORT MAP (
Clk => Clk,
Rst => Rst,
Output => Output
);
-- Clock process definitions
Clk_process :process
begin
Clk <= '0';
wait for Clk_period/2;
Clk <= '1';
wait for Clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
Rst <= '0';
wait for 100 ns;
Rst<= '1';
wait for Clk_period*10;
-- insert stimulus here
wait;
end process;
END;
想看到程序中间变量Clk1的波形，但是添加到wave中只会显示no data
C:\Users\WeiBin\Desktop\QQ截图20151113101756
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