library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity topmoudel is
Port ( clk : in std_logic;
a : in std_logic;
b : in std_logic;
reset:in std_logic;
output : out std_logic_vector(7 downto 0));
end topmoudel;
architecture Behavioral of topmoudel is
--signal bclk:std_logic;
type states is(statt1,statt2,statt3,statt4);
signal state:states:=statt1;
signal sum1:std_logic_vector(3 downto 0):="0000";
signal sum2:std_logic_vector(2 downto 0):="000";
signal sum3:std_logic_vector(1 downto 0):="00";
signal sum4:std_logic_vector(1 downto 0):="00";
--component testtt
--Port ( clk : in std_logic;
--reset : in std_logic;
--dout : out std_logic);
--end component;
begin
--u1:testtt
--port map(clk=>clk,reset=>reset,dout=>bclk);
process(reset,state,clk,a,b)
begin
if reset='1'then
case state is
when statt1=>
if (a='0'and b='0') then
if (clk'event and clk='1') then
sum1 <= sum1+'1';
end if;
end if;
when statt2=>
if (a='0'and b='1')then
if clk'event and clk='1'then
sum2<=sum2+'1';
end if;
end if;
when statt3=>
if (a='1'and b='0')then
if clk'event and clk='1'then
sum3<=sum3+'1';
end if;
end if;
when statt4=>
if (a='1'and b='1')then
if clk'event and clk='1'then
sum4<=sum4+'1';
end if;
end if;
end case;
end if;
end process;
process(sum1)
begin
case sum1 is
when "0001"=>output<="01000000";
when "0010"=>output<="00100000";
when "0011"=>output<="00010000";
when "0100"=>output<="00001000";
when "0101"=>output<="00000100";
when "0110"=>output<="00000010";
when "0111"=>output<="00000001";
when "1000"=>output<="00000010";
when "1001"=>output<="00000100";
when "1010"=>output<="00001000";
when "1011"=>output<="00010000";
when "1100"=>output<="00100000";
when "1101"=>output<="01000000";
when "1110"=>output<="10000000";
when others=>output<="10000000";
end case;
end process;
process(sum2)
begin
case sum2 is
when "001"=>output<="10000001";
when "010"=>output<="01000010";
when "011"=>output<="00100100";
when "100"=>output<="00011000";
when "101"=>output<="00100100";
when "110"=>output<="01000010";
when "111"=>output<="10000001";
when others=> output<="00000000";
end case;
end process;
process(sum3)
begin
case sum3 is
when "01"=>output<="11000011";
when "10"=>output<="00111100";
when "11"=>output<="11000011";
when others=>output<="11111111";
end case;
end process;
process(sum4)
begin
case sum4 is
when "01"=>output<="11111111";
when "10"=>output<="11110000";
when "11"=>output<="00001111";
when others=>output<="00000000";
end case;
end process;
end Behavioral;
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