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library IEEE; <br />use IEEE.STD_LOGIC_1164.ALL; <br />use IEEE.STD_LOGIC_ARITH.ALL; <br />use IEEE.STD_LOGIC_UNSIGNED.ALL; <br /><br />-- Uncomment the following lines to use the declarations that are <br />-- provided for instantiating Xilinx primitive components. <br />--library UNISIM; <br />--use UNISIM.VComponents.all; <br /><br />entity topmoudel is <br />Port ( clk : in std_logic; <br />a : in std_logic; <br />b : in std_logic; <br />reset:in std_logic; <br />output : out std_logic_vector(7 downto 0)); <br />end topmoudel; <br /><br />architecture Behavioral of topmoudel is <br />--signal bclk:std_logic; <br />type states is(statt1,statt2,statt3,statt4); <br />signal state:states:=statt1; <br />signal sum1:std_logic_vector(3 downto 0):="0000";<br />signal sum2:std_logic_vector(2 downto 0):="000"; <br />signal sum3:std_logic_vector(1 downto 0):="00"; <br />signal sum4:std_logic_vector(1 downto 0):="00"; <br /><br />--component testtt <br />--Port ( clk : in std_logic; <br />--reset : in std_logic; <br />--dout : out std_logic); <br />--end component; <br /><br />begin <br />--u1:testtt <br />--port map(clk=>clk,reset=>reset,dout=>bclk); <br />process(reset,state,clk,a,b) <br />begin <br />if reset='1'then <br />case state is <br /><br /> when statt1=> <br /> if (a='0'and b='0') then <br /> if (clk'event and clk='1') then <br /> sum1 <= sum1+'1';<br /> <br /> end if; <br /> end if; <br /><br /> when statt2=> <br /> if (a='0'and b='1')then <br /> if clk'event and clk='1'then <br /> sum2<=sum2+'1'; <br /> end if; <br /> end if; <br /><br /> when statt3=> <br /> if (a='1'and b='0')then <br /> if clk'event and clk='1'then <br /> sum3<=sum3+'1'; <br /> end if; <br /> end if; <br /><br /> when statt4=> <br /> if (a='1'and b='1')then <br /> if clk'event and clk='1'then <br /> sum4<=sum4+'1'; <br /> end if; <br /> end if; <br /><br /><br />end case; <br />end if; <br />end process; <br /><br /><br />process(sum1)<br />begin<br />case sum1 is <br /> when "0001"=>output<="01000000"; <br /> when "0010"=>output<="00100000"; <br /> when "0011"=>output<="00010000"; <br /> when "0100"=>output<="00001000"; <br /> when "0101"=>output<="00000100"; <br /> when "0110"=>output<="00000010"; <br /> when "0111"=>output<="00000001"; <br /> when "1000"=>output<="00000010"; <br /> when "1001"=>output<="00000100"; <br /> when "1010"=>output<="00001000"; <br /> when "1011"=>output<="00010000"; <br /> when "1100"=>output<="00100000"; <br /> when "1101"=>output<="01000000"; <br /> when "1110"=>output<="10000000"; <br /> when others=>output<="10000000"; <br /> end case;<br />end process;<br /><br /><br />process(sum2)<br />begin<br />case sum2 is <br />when "001"=>output<="10000001"; <br />when "010"=>output<="01000010"; <br />when "011"=>output<="00100100"; <br />when "100"=>output<="00011000"; <br />when "101"=>output<="00100100"; <br />when "110"=>output<="01000010"; <br />when "111"=>output<="10000001"; <br />when others=> output<="00000000"; <br />end case;<br />end process;<br /><br /><br />process(sum3)<br />begin<br />case sum3 is <br />when "01"=>output<="11000011"; <br />when "10"=>output<="00111100"; <br />when "11"=>output<="11000011"; <br />when others=>output<="11111111"; <br />end case; <br />end process;<br /><br /><br />process(sum4)<br />begin<br />case sum4 is <br />when "01"=>output<="11111111"; <br />when "10"=>output<="11110000"; <br />when "11"=>output<="00001111"; <br />when others=>output<="00000000"; <br />end case;<br />end process;<br /><br />end Behavioral; <br /><br /> |
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